whitequark c9879c795b build.{dsl,res,plat}: apply clock constraints to signals, not resources. ... This adds the Clock() build DSL element, and adds a resource manager function add_clock_constraint() that takes a Pin or a Signal. Note that not all platforms, in particular not any nextpnr platforms at the moment, can add constraints on arbitrary signals. Fixes #86.		2019-06-05 08:52:30 +00:00
..
back	back.rtlil: allow specifying platform for convert().	2019-05-26 17:10:56 +00:00
build	build.{dsl,res,plat}: apply clock constraints to signals, not resources.	2019-06-05 08:52:30 +00:00
compat	compat.fhdl.module: silence "unused elaboratable" warnings.	2019-06-04 13:09:36 +00:00
hdl	hdl.ir: rephrase elaboratable warning to not look like an error.	2019-06-04 13:11:15 +00:00
lib	Clean up imports.	2019-06-04 08:18:50 +00:00
test	build.{dsl,res,plat}: apply clock constraints to signals, not resources.	2019-06-05 08:52:30 +00:00
vendor	build.{dsl,res,plat}: apply clock constraints to signals, not resources.	2019-06-05 08:52:30 +00:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	Clean up imports.	2019-06-04 08:18:50 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00