whitequark ca6b1f2f1c lib.fifo: round up AsyncFIFO{,Buffered} depth to lowest valid value. ... Unless exact_depth=True is specified. The logic introduced in this commit is idempotent: that is, if one uses the depth of one AsyncFIFOBuffered in the constructor of another AsyncFIFOBuffered, they will end up with the same depth. More naive logic would result in an unbounded, quadratic growth with each such step. Fixes #219.		2019-09-23 10:58:20 +00:00
..
back	hdl.ast: rename nbits to width.	2019-09-20 15:36:25 +00:00
build	build.plat: restrict design names to alphanumeric to avoid quoting issues.	2019-09-22 06:57:28 +00:00
compat	lib.fifo: make simulation read() and write() functions compat-only.	2019-09-23 08:46:12 +00:00
hdl	hdl.rec: fix using Enum subclass as shape if direction is specified.	2019-09-22 17:23:32 +00:00
lib	lib.fifo: round up AsyncFIFO{,Buffered} depth to lowest valid value.	2019-09-23 10:58:20 +00:00
test	lib.fifo: round up AsyncFIFO{,Buffered} depth to lowest valid value.	2019-09-23 10:58:20 +00:00
vendor	vendor.lattice_ice40: fix required tool list for iCECube2. NFC.	2019-09-22 07:18:37 +00:00
__init__.py	Remove nmigen.lib from prelude.	2019-09-06 06:53:06 +00:00
_toolchain.py	_toolchain,build.plat,vendor.*: add required_tools list and checks.	2019-08-31 00:05:47 +00:00
asserts.py	hdl.ast,back.rtlil: implement Cover.	2019-09-03 01:32:24 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: fix typo.	2019-08-19 20:20:18 +00:00