| .. |
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compat
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_tools: extract most utility methods to a private package.
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2019-10-12 22:40:48 +00:00 |
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__init__.py
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hdl.ir: detect elaboratables that are created but not used.
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2019-04-21 08:52:57 +00:00 |
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test_build_dsl.py
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build.dsl: accept Pins(invert=True).
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2019-10-03 02:44:43 +00:00 |
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test_build_res.py
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build.res: simplify clock constraints.
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2019-09-21 14:12:29 +00:00 |
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test_compat.py
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compat.fhdl.module: CompatModule should be elaboratable.
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2019-06-04 11:11:31 +00:00 |
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test_examples.py
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test.test_examples: Convert pathlib-specific class to string.
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2019-08-20 00:54:10 +00:00 |
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test_hdl_ast.py
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hdl.ast: rename Slice.end back to Slice.stop.
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2019-10-12 22:40:48 +00:00 |
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test_hdl_cd.py
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hdl.cd: add negedge clock domains.
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2019-08-31 22:05:48 +00:00 |
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test_hdl_dsl.py
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hdl.ast: deprecate Signal.{range,enum}.
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2019-10-11 13:07:42 +00:00 |
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test_hdl_ir.py
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hdl.ir: allow ClockSignal and ResetSignal in ports.
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2019-10-13 03:39:56 +00:00 |
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test_hdl_mem.py
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Consistently use {!r}, not '{!r}' in diagnostics.
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2019-10-11 11:47:42 +00:00 |
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test_hdl_rec.py
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Rename remaining wrap methods to cast.
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2019-10-11 13:28:26 +00:00 |
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test_hdl_xfrm.py
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hdl.xfrm: lower resets in DomainLowerer as well.
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2019-08-19 21:44:30 +00:00 |
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test_lib_cdc.py
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Consistently use {!r}, not '{!r}' in diagnostics.
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2019-10-11 11:47:42 +00:00 |
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test_lib_coding.py
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formal→asserts
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2019-08-19 20:23:24 +00:00 |
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test_lib_fifo.py
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hdl.ast: deprecate Signal.{range,enum}.
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2019-10-11 13:07:42 +00:00 |
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test_lib_io.py
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Clean up imports.
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2019-06-04 08:18:50 +00:00 |
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test_sim.py
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_tools: extract most utility methods to a private package.
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2019-10-12 22:40:48 +00:00 |
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tools.py
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Rename remaining wrap methods to cast.
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2019-10-11 13:28:26 +00:00 |
