Wanda 1d2b9c309e back.rtlil: set read port init to all-x. ... This is an unfortunate necessity needed to fix memory inference regressions introduced when we switched to using v2 cells. A better approach, compatible with RFC 54, will need to be figured out for Amaranth 0.6. Fixes #1011.		2024-05-09 02:38:53 +00:00
..
__init__.py	Rename nMigen to Amaranth HDL.	2021-12-10 10:34:13 +00:00
cxxrtl.py	Pyupgrade to 3.8+. NFCI	2023-11-14 13:07:21 +00:00
rtlil.py	back.rtlil: set read port init to all-x.	2024-05-09 02:38:53 +00:00
verilog.py	back.verilog, back.rtlil: map path elements to str	2024-04-19 21:54:23 +00:00