whitequark d0ac8bf789 back.rtlil: actually match shape of left hand side. ... This comes up in code such as: Array([Signal(1), Signal(8)]).eq(Const(0, 8))		2019-08-03 23:48:28 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.ast: deprecate Value.part, add Value.{bit,word}_select.	2019-08-03 13:07:06 +00:00
rtlil.py	back.rtlil: actually match shape of left hand side.	2019-08-03 23:48:28 +00:00
verilog.py	back.verilog: run proc_prune for much cleaner output.	2019-07-09 19:28:09 +00:00