Catherine da26f1c915 hdl,back,sim: accept .as_signed() and .as_unsigned() on LHS. ... These operators are ignored when they are encountered on LHS, as the signedness of the assignment target does not matter in Amaranth. .as_signed() appears on LHS of assigns to signed aggregate fields.		2022-09-24 07:19:47 +00:00
..
__init__.py	Rename nMigen to Amaranth HDL.	2021-12-10 10:34:13 +00:00
_base.py	Rename nMigen to Amaranth HDL.	2021-12-10 10:34:13 +00:00
_pyclock.py	sim: represent time internally as 1ps units	2021-12-13 08:15:11 +00:00
_pycoro.py	sim: represent time internally as 1ps units	2021-12-13 08:15:11 +00:00
_pyrtl.py	hdl,back,sim: accept .as_signed() and .as_unsigned() on LHS.	2022-09-24 07:19:47 +00:00
core.py	sim: Fix clock phase in add_clock having to be specified in ps.	2022-02-04 16:46:52 +00:00
pysim.py	sim.pysim: use "bench" as a top level root for testbench signals.	2021-12-16 15:46:05 +00:00