8.6 KiB
Migen and nMigen compatibility summary
nMigen intends to provide as close to 100% compatibility to Migen as possible without compromising its other goals. However, Migen widely uses * imports, tends to expose implementation details, and in general does not have a well-defined interface. This document attempts to elucidate a well-defined Migen API surface (including, when necessary, private items that have been used downstream), and describes the intended nMigen replacements and their implementation status.
API change legend:
- id: identical
- obs: removed or irreversibly changed with compatibility stub provided
- obs →n: removed or irreversibly changed with compatibility stub provided, use n instead
- brk: removed or irreversibly changed with no replacement provided
- brk →n: removed or irreversibly changed with no replacement provided, use n instead
- →n: renamed to n
- ⇒m: merged into m
- a=→b=: parameter a renamed to b
- a=∼: parameter a removed
- .a=→.b: attribute a renamed to b
- .a=∼: attribute a removed
- ?: no decision made yet
When describing renames or replacements, mod refers to a 3rd-party package mod (no nMigen implementation provided), .mod.item refers to nmigen.mod.item, and "(import .item)" means that, while item is provided under nmigen.mod.item, it is aliased to, and should be imported from a shorter path for readability.
Status legend:
- (−) No decision yet, or no replacement implemented
- (+) Implemented replacement (the API and/or compatibility shim are provided)
- (⊕) Verified replacement and/or compatibility shim (the compatibility shim is manually reviewed and/or has 100% test coverage)
- (⊙) No direct replacement or compatibility shim is provided
Compatibility summary
- (−)
fhdl→.hdl- (+)
bitcontainer⇒.tools- (+)
log2_intid - (+)
bits_forid - (+)
value_bits_sign→Value.shape
- (+)
- (−)
conv_output? - (+)
decorators⇒.hdl.xfrm
Note:transform_*methods not considered part of public API.- (⊙)
ModuleTransformerbrk - (⊙)
ControlInserterbrk - (-)
CEInserterobs - (-)
ResetInserterobs - (+)
ClockDomainsRenamer→DomainRenamer,cd_remapping=→domain_map=
- (⊙)
- (⊙)
edifbrk - (+)
moduleobs →.hdl.dsl- (+)
FinalizeErrorobs - (+)
Moduleobs →.hdl.dsl.Module
- (+)
- (⊙)
namerbrk - (−)
simplify?- (−)
FullMemoryWE? - (−)
MemoryToArray? - (−)
SplitMemory?
- (−)
- (⊕)
specialsobs- (⊙)
Specialbrk - (⊕)
Tristate→.lib.io.Tristate,target=→io= - (⊕)
TSTriple→.lib.io.TSTriple,bits_sign=→shape= - (⊕)
Instance→.hdl.ir.Instance - (⊕)
Memoryid- (⊕)
.get_portobs →.read_port()+.write_port()
- (⊕)
- (⊕)
_MemoryPortobs
Note: nMigen separates read and write ports. - (⊕)
READ_FIRST/WRITE_FIRSTobs
Note:READ_FIRSTcorresponds tomem.read_port(transparent=False), andWRITE_FIRSTtomem.read_port(transparent=True). - (⊙)
NO_CHANGEbrk
Note: in designs usingNO_CHANGE, repalce it with an asynchronous read port and logic implementing required semantics explicitly.
- (⊙)
- (−)
structure→.hdl.ast- (+)
DUIDid - (+)
_Value→Value
Note: values no longer valid as keys indictandset; useValueDictandValueSetinstead. - (+)
wrap→Value.wrap - (+)
_Operator→Operator - (+)
Muxid - (+)
_Slice→Slice,stop=→end=,.stop→.end - (+)
_Part→Part - (+)
Catid,.l→.parts - (+)
Replicate→Repl,v=→value=,n=→count=,.v→.value,.n→.count - (+)
Constant→Const,bits_sign=→shape= - (+)
Signalid,bits_sign=→shape=,attr=→attrs=,name_override=∼,related=,variable=∼ - (+)
ClockSignalid,cd=→domain= - (+)
ResetSignalid,cd=→domain= - (+)
_Statement→Statement - (+)
_Assign→Assign,l=→lhs=,r=→rhs= - (+)
_check_statementobs →Statement.wrap - (+)
Ifobs →.hdl.dsl.Module.If - (+)
Caseobs →.hdl.dsl.Module.Switch - (+)
_ArrayProxy→.hdl.ast.ArrayProxy,choices=→elems=,key=→index= - (+)
Arrayid - (+)
ClockDomain→.hdl.cd.ClockDomain - (−)
_ClockDomainList? - (−)
SPECIAL_INPUT/SPECIAL_OUTPUT/SPECIAL_INOUT? - (⊙)
_Fragmentbrk →.hdl.ir.Fragment
- (+)
- (−)
toolsbrk- (−)
list_signals? - (−)
list_targets? - (−)
list_inputs? - (−)
group_by_targets? - (⊙)
list_special_iosbrk - (⊙)
list_clock_domains_exprbrk - (−)
list_clock_domains? - (−)
is_variable? - (⊙)
generate_resetbrk - (⊙)
insert_resetbrk - (⊙)
insert_resetsbrk →.hdl.xfrm.ResetInserter - (⊙)
lower_basicsbrk - (⊙)
lower_complex_slicesbrk - (⊙)
lower_complex_partsbrk - (⊙)
rename_clock_domain_exprbrk - (⊙)
rename_clock_domainbrk →.hdl.xfrm.DomainRenamer - (⊙)
call_special_classmethodbrk - (⊙)
lower_specialsbrk
- (−)
- (−)
tracerbrk- (−)
get_var_name? - (−)
remove_underscore? - (−)
get_obj_var_name? - (−)
index_id? - (−)
trace_back?
- (−)
- (−)
verilog- (−)
DummyAttrTranslate? - (−)
convertobs →.back.verilog.convert
- (−)
- (⊙)
visitbrk →.hdl.xfrm- (⊙)
NodeVisitorbrk - (⊙)
NodeTransformerbrk →.hdl.xfrm.ValueTransformer/.hdl.xfrm.StatementTransformer
- (⊙)
- (+)
- (−)
genlib→.lib- (−)
cdc?- (−)
MultiRegImpl? - (⊕)
MultiRegid - (−)
PulseSynchronizer? - (−)
BusSynchronizer? - (⊕)
GrayCounterobs →.lib.coding.GrayEncoder - (⊕)
GrayDecoderobs →.lib.coding.GrayDecoder
Note:.lib.coding.GrayEncoderand.lib.coding.GrayDecoderare purely combinatorial. - (−)
ElasticBuffer? - (−)
lcm? - (−)
Gearbox?
- (−)
- (⊕)
codingid- (⊕)
Encoderid - (⊕)
PriorityEncoderid - (⊕)
Decoderid - (⊕)
PriorityDecoderid
- (⊕)
- (−)
divider?- (−)
Divider?
- (−)
- (−)
fifo?- (⊕)
_FIFOInterface→FIFOInterface - (⊕)
SyncFIFOid,.fifo=∼ - (⊕)
SyncFIFOBufferedid,.fifo=∼ - (−)
AsyncFIFO? - (−)
AsyncFIFOBuffered?
- (⊕)
- (+)
fsmobs- (+)
AnonymousStateobs - (+)
NextStateobs - (+)
NextValueobs - (+)
_LowerNextobs - (+)
FSMobs
- (+)
- (−)
io?- (−)
DifferentialInput? - (−)
DifferentialOutput? - (−)
CRG? - (−)
DDRInput? - (−)
DDROutput?
- (−)
- (−)
misc?- (−)
split? - (−)
displacer? - (−)
chooser? - (−)
timeline? - (−)
WaitTimer? - (−)
BitSlip?
- (−)
- (−)
recordobs →.hdl.rec.Record- (−)
DIR_NONEid - (−)
DIR_M_TO_S→DIR_FANOUT - (−)
DIR_S_TO_M→DIR_FANIN - (−)
set_layout_parametersbrk - (−)
layout_lenbrk - (−)
layout_getbrk - (−)
layout_partialbrk - (−)
Recordid
- (−)
- (+)
resetsync?- (+)
AsyncResetSynchronizerobs →.lib.cdc.ResetSynchronizer
- (+)
- (−)
roundrobin?- (−)
SP_WITHDRAW/SP_CE? - (−)
RoundRobin?
- (−)
- (−)
sort?- (−)
BitonicSort?
- (−)
- (−)
- (-)
simobs →.back.pysim
Note: only items directly undernmigen.compat.sim, not submodules, are provided.- (⊙)
corebrk - (⊙)
vcdbrk →vcd - (⊙)
Simulatorbrk - (⊕)
run_simulationobs →.back.pysim.Simulator - (⊕)
passiveobs →.hdl.ast.Passive
- (⊙)
- (−)
build? - (+)
utilobs- (+)
misc⇒.tools- (+)
flat_iteration→.flatten - (⊙)
xdirbrk - (⊙)
gcd_multiplebrk
- (+)
- (⊙)
treevizbrk
- (+)