Alyssa Rosenzweig c83b51db6d back.verilog: Fix strip_internal_attrs ... Fix the strip_internal_attrs parameter to verilog.convert by passing it down the call stack as intended. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>		2022-01-27 06:42:59 +00:00
..
__init__.py	Rename nMigen to Amaranth HDL.	2021-12-10 10:34:13 +00:00
cxxrtl.py	hdl.ast: support division and modulo with negative divisor.	2021-12-11 10:25:48 +00:00
pysim.py	Rename nMigen to Amaranth HDL.	2021-12-10 10:34:13 +00:00
rtlil.py	back.rtlil: avoid sync process emission in RTLIL.	2022-01-01 18:18:33 +00:00
verilog.py	back.verilog: Fix strip_internal_attrs	2022-01-27 06:42:59 +00:00