Jean-François Nguyen dd5bd1c88d build: add DSL for defining platform resources.		2019-04-24 11:49:01 +00:00
..
back	back.verilog: allow stripping the src attribute, for cleaner output.	2019-04-22 14:59:53 +00:00
build	build: add DSL for defining platform resources.	2019-04-24 11:49:01 +00:00
compat	compat.fhdl.specials: fix Tristate, TSTriple.	2019-04-22 09:57:12 +00:00
hdl	hdl.ir: rework named port handling for Instances.	2019-04-22 07:46:47 +00:00
lib	hdl.ir: detect elaboratables that are created but not used.	2019-04-21 08:52:57 +00:00
test	build: add DSL for defining platform resources.	2019-04-24 11:49:01 +00:00
__init__.py	hdl.ir: detect elaboratables that are created but not used.	2019-04-21 08:52:57 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	formal: extract from toplevel module.	2019-01-17 01:43:07 +00:00
tools.py	compat: suppress deprecation warnings that are internal or during test.	2019-01-26 15:43:00 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00