112 lines
4.5 KiB
Python
112 lines
4.5 KiB
Python
from ..build.dsl import *
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from .tools import *
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class PinsTestCase(FHDLTestCase):
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def test_basic(self):
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p = Pins("A0 A1 A2")
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self.assertEqual(repr(p), "(pins A0 A1 A2 io)")
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self.assertEqual(len(p.names), 3)
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self.assertEqual(p.dir, "io")
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def test_wrong_names(self):
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with self.assertRaises(TypeError,
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msg="Names must be a whitespace-separated string, not ['A0', 'A1', 'A2']"):
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p = Pins(["A0", "A1", "A2"])
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def test_wrong_dir(self):
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with self.assertRaises(TypeError,
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msg="Direction must be one of \"i\", \"o\" or \"io\", not 'wrong'"):
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p = Pins("A0 A1", dir="wrong")
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class DiffPairsTestCase(FHDLTestCase):
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def test_basic(self):
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dp = DiffPairs(p="A0 A1", n="B0 B1")
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self.assertEqual(repr(dp), "(diffpairs (pins A0 A1 io) (pins B0 B1 io))")
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self.assertEqual(dp.p.names, ["A0", "A1"])
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self.assertEqual(dp.n.names, ["B0", "B1"])
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self.assertEqual(dp.dir, "io")
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def test_dir(self):
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dp = DiffPairs("A0", "B0", dir="o")
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self.assertEqual(dp.dir, "o")
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self.assertEqual(dp.p.dir, "o")
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self.assertEqual(dp.n.dir, "o")
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def test_wrong_width(self):
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with self.assertRaises(TypeError,
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msg="Positive and negative pins must have the same width, but (pins A0 io) and "
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"(pins B0 B1 io) do not"):
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dp = DiffPairs("A0", "B0 B1")
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class SubsignalTestCase(FHDLTestCase):
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def test_basic_pins(self):
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s = Subsignal("a", Pins("A0"), extras=["IOSTANDARD=LVCMOS33"])
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self.assertEqual(repr(s), "(subsignal a (pins A0 io) IOSTANDARD=LVCMOS33)")
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def test_basic_diffpairs(self):
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s = Subsignal("a", DiffPairs("A0", "B0"))
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self.assertEqual(repr(s), "(subsignal a (diffpairs (pins A0 io) (pins B0 io)) )")
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def test_basic_subsignals(self):
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s = Subsignal("a",
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Subsignal("b", Pins("A0")),
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Subsignal("c", Pins("A1")))
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self.assertEqual(repr(s),
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"(subsignal a (subsignal b (pins A0 io) ) (subsignal c (pins A1 io) ) )")
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def test_extras(self):
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s = Subsignal("a",
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Subsignal("b", Pins("A0")),
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Subsignal("c", Pins("A0"), extras=["SLEW=FAST"]),
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extras=["IOSTANDARD=LVCMOS33"])
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self.assertEqual(s.extras, ["IOSTANDARD=LVCMOS33"])
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self.assertEqual(s.io[0].extras, ["IOSTANDARD=LVCMOS33"])
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self.assertEqual(s.io[1].extras, ["SLEW=FAST", "IOSTANDARD=LVCMOS33"])
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def test_empty_io(self):
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with self.assertRaises(TypeError, msg="Missing I/O constraints"):
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s = Subsignal("a")
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def test_wrong_io(self):
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with self.assertRaises(TypeError,
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msg="I/O constraint must be one of Pins, DiffPairs or Subsignal, not 'wrong'"):
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s = Subsignal("a", "wrong")
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def test_wrong_pins(self):
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with self.assertRaises(TypeError,
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msg="Pins and DiffPairs cannot be followed by more I/O constraints, but "
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"(pins A0 io) is followed by (pins A1 io)"):
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s = Subsignal("a", Pins("A0"), Pins("A1"))
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def test_wrong_diffpairs(self):
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with self.assertRaises(TypeError,
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msg="Pins and DiffPairs cannot be followed by more I/O constraints, but "
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"(diffpairs (pins A0 io) (pins B0 io)) is followed by (pins A1 io)"):
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s = Subsignal("a", DiffPairs("A0", "B0"), Pins("A1"))
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def test_wrong_subsignals(self):
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with self.assertRaises(TypeError,
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msg="A Subsignal can only be followed by more Subsignals, but "
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"(subsignal b (pins A0 io) ) is followed by (pins B0 io)"):
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s = Subsignal("a", Subsignal("b", Pins("A0")), Pins("B0"))
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def test_wrong_extras(self):
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with self.assertRaises(TypeError,
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msg="Extra constraint must be a string, not (pins B0 io)"):
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s = Subsignal("a", Pins("A0"), extras=[Pins("B0")])
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class ResourceTestCase(FHDLTestCase):
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def test_basic(self):
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r = Resource("serial", 0,
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Subsignal("tx", Pins("A0", dir="o")),
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Subsignal("rx", Pins("A1", dir="i")),
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extras=["IOSTANDARD=LVCMOS33"])
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self.assertEqual(repr(r), "(resource serial 0"
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" (subsignal tx (pins A0 o) IOSTANDARD=LVCMOS33)"
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" (subsignal rx (pins A1 i) IOSTANDARD=LVCMOS33)"
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" IOSTANDARD=LVCMOS33)")
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