whitequark dd5e513e42 back.rtlil: do not emit $next wires for comb signals. ... According to RTLIL semantics (that was undocumented before today), the only purpose of `sync always` is to enable inference of latches, because there is no other way to express them in terms of RTLIL processes without ending up with a combinatorial loop. But, nMigen specifically avoids latches, so this is not necessary. This change results in major improvements in Verilog readability. See also #98.		2019-07-02 18:05:34 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: create unique ResetSynchronizer internal domains.	2019-06-28 08:34:43 +00:00
rtlil.py	back.rtlil: do not emit $next wires for comb signals.	2019-07-02 18:05:34 +00:00
verilog.py	back.verilog: allow stripping the src attribute, for cleaner output.	2019-04-22 14:59:53 +00:00