whitequark dd5e513e42 back.rtlil: do not emit $next wires for comb signals. ... According to RTLIL semantics (that was undocumented before today), the only purpose of `sync always` is to enable inference of latches, because there is no other way to express them in terms of RTLIL processes without ending up with a combinatorial loop. But, nMigen specifically avoids latches, so this is not necessary. This change results in major improvements in Verilog readability. See also #98.		2019-07-02 18:05:34 +00:00
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back	back.rtlil: do not emit $next wires for comb signals.	2019-07-02 18:05:34 +00:00
build	build.plat: fix dedent overrides.	2019-06-28 06:52:52 +00:00
compat	hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.	2019-06-28 04:37:08 +00:00
hdl	hdl.rec: implement slicing by component names.	2019-07-02 17:46:53 +00:00
lib	hdl.mem: use read_port(domain="comb") for asynchronous read ports.	2019-07-01 19:56:49 +00:00
test	hdl.rec: implement slicing by component names.	2019-07-02 17:46:53 +00:00
vendor	vendor.xilinx_7series: read extra .xdc files.	2019-07-02 08:23:37 +00:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	Clean up imports.	2019-06-04 08:18:50 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00