whitequark e3a1d05f23 back.rtlil: fix handling of certain nested arrays. ... This triggers on code like: c1 = Signal() c2 = Signal() c3 = Signal() v1 = Array([Const(1, 8), Const(2, 8)])[c1] v2 = Array([Const(3, 8), Const(4, 8)])[c2] v3 = Array([v1, v2])[c3] Fixes #226.		2019-09-24 18:32:26 +00:00
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back	back.rtlil: fix handling of certain nested arrays.	2019-09-24 18:32:26 +00:00
build	build.plat: strip internal attributes from Verilog output.	2019-09-24 14:56:00 +00:00
compat	lib.cdc: MultiReg→FFSynchronizer.	2019-09-23 14:18:45 +00:00
hdl	hdl.ast: cast Mux() selector to bool if it is not a 1-bit value.	2019-09-23 13:39:31 +00:00
lib	build.plat,lib.cdc,vendor: unify platform related diagnostics. NFC.	2019-09-24 14:14:45 +00:00
test	lib.cdc: add diagnostic checks for synchronization stage count.	2019-09-23 19:38:21 +00:00
vendor	build.plat: strip internal attributes from Verilog output.	2019-09-24 14:56:00 +00:00
__init__.py	Remove nmigen.lib from prelude.	2019-09-06 06:53:06 +00:00
_toolchain.py	_toolchain,build.plat,vendor.*: add required_tools list and checks.	2019-08-31 00:05:47 +00:00
asserts.py	hdl.ast,back.rtlil: implement Cover.	2019-09-03 01:32:24 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: fix typo.	2019-08-19 20:20:18 +00:00