53bb4300a3
Although useful for debugging, most external tools often complain about such attributes (with notable exception of Vivado). As such, it is better to emit Verilog with these attributes into a separate file such as `design.debug.v` and only emit the attributes that were explicitly placed by the user to `design.v`. This still leaves the (*init*) attribute. See #220 for details.
369 lines
14 KiB
Python
369 lines
14 KiB
Python
from collections import OrderedDict
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from abc import ABCMeta, abstractmethod, abstractproperty
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import os
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import textwrap
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import re
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import jinja2
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from .. import __version__
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from .._toolchain import *
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from ..hdl.ast import *
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from ..hdl.cd import *
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from ..hdl.dsl import *
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from ..hdl.ir import *
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from ..back import rtlil, verilog
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from .res import *
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from .run import *
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__all__ = ["Platform", "TemplatedPlatform"]
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class Platform(ResourceManager, metaclass=ABCMeta):
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resources = abstractproperty()
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connectors = abstractproperty()
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default_clk = None
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default_rst = None
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required_tools = abstractproperty()
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def __init__(self):
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super().__init__(self.resources, self.connectors)
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self.extra_files = OrderedDict()
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self._prepared = False
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@property
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def default_clk_constraint(self):
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if self.default_clk is None:
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raise AttributeError("Platform '{}' does not define a default clock"
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.format(type(self).__name__))
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return self.lookup(self.default_clk).clock
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@property
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def default_clk_frequency(self):
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constraint = self.default_clk_constraint
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if constraint is None:
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raise AttributeError("Platform '{}' does not constrain its default clock"
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.format(type(self).__name__))
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return constraint.frequency
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def add_file(self, filename, content):
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if not isinstance(filename, str):
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raise TypeError("File name must be a string")
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if filename in self.extra_files:
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raise ValueError("File {} already exists"
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.format(filename))
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if hasattr(content, "read"):
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content = content.read()
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elif not isinstance(content, (str, bytes)):
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raise TypeError("File contents must be str, bytes, or a file-like object")
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self.extra_files[filename] = content
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@property
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def _toolchain_env_var(self):
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return f"NMIGEN_ENV_{self.toolchain}"
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def build(self, elaboratable, name="top",
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build_dir="build", do_build=True,
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program_opts=None, do_program=False,
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**kwargs):
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if self._toolchain_env_var not in os.environ:
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for tool in self.required_tools:
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require_tool(tool)
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plan = self.prepare(elaboratable, name, **kwargs)
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if not do_build:
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return plan
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products = plan.execute_local(build_dir)
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if not do_program:
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return products
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self.toolchain_program(products, name, **(program_opts or {}))
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def has_required_tools(self):
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if self._toolchain_env_var in os.environ:
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return True
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return all(has_tool(name) for name in self.required_tools)
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@abstractmethod
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def create_missing_domain(self, name):
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# Simple instantiation of a clock domain driven directly by the board clock and reset.
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# Because of device-specific considerations, this implementation generally does NOT provide
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# reliable power-on/post-configuration reset, and the logic should be replaced with family
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# specific logic based on vendor recommendations.
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if name == "sync" and self.default_clk is not None:
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clk_i = self.request(self.default_clk).i
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if self.default_rst is not None:
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rst_i = self.request(self.default_rst).i
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m = Module()
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m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
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m.d.comb += ClockSignal("sync").eq(clk_i)
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if self.default_rst is not None:
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m.d.comb += ResetSignal("sync").eq(rst_i)
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return m
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def prepare(self, elaboratable, name="top", **kwargs):
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assert not self._prepared
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self._prepared = True
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fragment = Fragment.get(elaboratable, self)
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fragment.create_missing_domains(self.create_missing_domain)
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def add_pin_fragment(pin, pin_fragment):
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pin_fragment = Fragment.get(pin_fragment, self)
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if not isinstance(pin_fragment, Instance):
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pin_fragment.flatten = True
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fragment.add_subfragment(pin_fragment, name="pin_{}".format(pin.name))
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for pin, port, attrs, invert in self.iter_single_ended_pins():
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if pin.dir == "i":
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add_pin_fragment(pin, self.get_input(pin, port, attrs, invert))
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if pin.dir == "o":
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add_pin_fragment(pin, self.get_output(pin, port, attrs, invert))
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if pin.dir == "oe":
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add_pin_fragment(pin, self.get_tristate(pin, port, attrs, invert))
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if pin.dir == "io":
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add_pin_fragment(pin, self.get_input_output(pin, port, attrs, invert))
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for pin, p_port, n_port, attrs, invert in self.iter_differential_pins():
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if pin.dir == "i":
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add_pin_fragment(pin, self.get_diff_input(pin, p_port, n_port, attrs, invert))
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if pin.dir == "o":
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add_pin_fragment(pin, self.get_diff_output(pin, p_port, n_port, attrs, invert))
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if pin.dir == "oe":
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add_pin_fragment(pin, self.get_diff_tristate(pin, p_port, n_port, attrs, invert))
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if pin.dir == "io":
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add_pin_fragment(pin,
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self.get_diff_input_output(pin, p_port, n_port, attrs, invert))
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fragment = fragment.prepare(ports=self.iter_ports(), missing_domain=lambda name: None)
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return self.toolchain_prepare(fragment, name, **kwargs)
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@abstractmethod
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def toolchain_prepare(self, fragment, name, **kwargs):
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"""
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Convert the ``fragment`` and constraints recorded in this :class:`Platform` into
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a :class:`BuildPlan`.
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"""
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raise NotImplementedError # :nocov:
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def toolchain_program(self, products, name, **kwargs):
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"""
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Extract bitstream for fragment ``name`` from ``products`` and download it to a target.
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"""
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raise NotImplementedError("Platform '{}' does not support programming"
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.format(type(self).__name__))
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def _check_feature(self, feature, pin, attrs, valid_xdrs, valid_attrs):
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if not valid_xdrs:
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raise NotImplementedError("Platform '{}' does not support {}"
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.format(type(self).__name__, feature))
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elif pin.xdr not in valid_xdrs:
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raise NotImplementedError("Platform '{}' does not support {} for XDR {}"
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.format(type(self).__name__, feature, pin.xdr))
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if not valid_attrs and attrs:
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raise NotImplementedError("Platform '{}' does not support attributes for {}"
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.format(type(self).__name__, feature))
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@staticmethod
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def _invert_if(invert, value):
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if invert:
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return ~value
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else:
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return value
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def get_input(self, pin, port, attrs, invert):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0,), valid_attrs=None)
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m = Module()
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m.d.comb += pin.i.eq(self._invert_if(invert, port))
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return m
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def get_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0,), valid_attrs=None)
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m = Module()
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m.d.comb += port.eq(self._invert_if(invert, pin.o))
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return m
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def get_tristate(self, pin, port, attrs, invert):
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0,), valid_attrs=None)
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m = Module()
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m.submodules += Instance("$tribuf",
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p_WIDTH=pin.width,
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i_EN=pin.oe,
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i_A=self._invert_if(invert, pin.o),
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o_Y=port,
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)
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return m
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def get_input_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0,), valid_attrs=None)
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m = Module()
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m.submodules += Instance("$tribuf",
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p_WIDTH=pin.width,
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i_EN=pin.oe,
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i_A=self._invert_if(invert, pin.o),
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o_Y=port,
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)
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m.d.comb += pin.i.eq(self._invert_if(invert, port))
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return m
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def get_diff_input(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(), valid_attrs=None)
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def get_diff_output(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(), valid_attrs=None)
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def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential tristate", pin, attrs,
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valid_xdrs=(), valid_attrs=None)
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def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential input/output", pin, attrs,
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valid_xdrs=(), valid_attrs=None)
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class TemplatedPlatform(Platform):
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toolchain = abstractproperty()
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file_templates = abstractproperty()
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command_templates = abstractproperty()
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build_script_templates = {
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"build_{{name}}.sh": """
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# {{autogenerated}}
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set -e{{verbose("x")}}
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[ -n "${{platform._toolchain_env_var}}" ] && . "${{platform._toolchain_env_var}}"
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{{emit_commands("sh")}}
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""",
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"build_{{name}}.bat": """
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@rem {{autogenerated}}
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{{quiet("@echo off")}}
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if defined {{platform._toolchain_env_var}} call %{{platform._toolchain_env_var}}%
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{{emit_commands("bat")}}
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""",
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}
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def toolchain_prepare(self, fragment, name, **kwargs):
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# Restrict the name of the design to a strict alphanumeric character set. Platforms will
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# interpolate the name of the design in many different contexts: filesystem paths, Python
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# scripts, Tcl scripts, ad-hoc constraint files, and so on. It is not practical to add
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# escaping code that handles every one of their edge cases, so make sure we never hit them
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# in the first place.
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invalid_char = re.match(r"[^A-Za-z0-9_]", name)
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if invalid_char:
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raise ValueError("Design name {!r} contains invalid character {!r}; only alphanumeric "
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"characters are valid in design names"
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.format(name, invalid_char.group(0)))
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# This notice serves a dual purpose: to explain that the file is autogenerated,
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# and to incorporate the nMigen version into generated code.
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autogenerated = "Automatically generated by nMigen {}. Do not edit.".format(__version__)
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rtlil_text, name_map = rtlil.convert_fragment(fragment, name=name)
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def emit_rtlil():
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return rtlil_text
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def emit_verilog():
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return verilog._convert_rtlil_text(rtlil_text, strip_internal_attrs=True)
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def emit_debug_verilog():
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return verilog._convert_rtlil_text(rtlil_text, strip_internal_attrs=False)
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def emit_commands(format):
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commands = []
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for index, command_tpl in enumerate(self.command_templates):
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command = render(command_tpl, origin="<command#{}>".format(index + 1))
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command = re.sub(r"\s+", " ", command)
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if format == "sh":
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commands.append(command)
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elif format == "bat":
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commands.append(command + " || exit /b")
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else:
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assert False
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return "\n".join(commands)
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def get_override(var):
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var_env = "NMIGEN_{}".format(var)
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if var_env in os.environ:
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# On Windows, there is no way to define an "empty but set" variable; it is tempting
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# to use a quoted empty string, but it doesn't do what one would expect. Recognize
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# this as a useful pattern anyway, and treat `set VAR=""` on Windows the same way
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# `export VAR=` is treated on Linux.
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return re.sub(r'^\"\"$', "", os.environ[var_env])
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elif var in kwargs:
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if isinstance(kwargs[var], str):
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return textwrap.dedent(kwargs[var]).strip()
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else:
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return kwargs[var]
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else:
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return jinja2.Undefined(name=var)
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def options(opts):
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if isinstance(opts, str):
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return opts
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else:
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return " ".join(opts)
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def hierarchy(signal, separator):
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return separator.join(name_map[signal][1:])
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def verbose(arg):
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if "NMIGEN_verbose" in os.environ:
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return arg
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else:
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return jinja2.Undefined(name="quiet")
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def quiet(arg):
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if "NMIGEN_verbose" in os.environ:
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return jinja2.Undefined(name="quiet")
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else:
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return arg
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def render(source, origin):
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try:
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source = textwrap.dedent(source).strip()
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compiled = jinja2.Template(source, trim_blocks=True, lstrip_blocks=True)
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compiled.environment.filters["options"] = options
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compiled.environment.filters["hierarchy"] = hierarchy
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except jinja2.TemplateSyntaxError as e:
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e.args = ("{} (at {}:{})".format(e.message, origin, e.lineno),)
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raise
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return compiled.render({
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"name": name,
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"platform": self,
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"emit_rtlil": emit_rtlil,
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"emit_verilog": emit_verilog,
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"emit_debug_verilog": emit_debug_verilog,
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"emit_commands": emit_commands,
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"get_tool": get_tool,
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"get_override": get_override,
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"verbose": verbose,
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"quiet": quiet,
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"autogenerated": autogenerated,
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})
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plan = BuildPlan(script="build_{}".format(name))
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for filename_tpl, content_tpl in self.file_templates.items():
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plan.add_file(render(filename_tpl, origin=filename_tpl),
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render(content_tpl, origin=content_tpl))
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for filename, content in self.extra_files.items():
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plan.add_file(filename, content)
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return plan
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def iter_extra_files(self, *endswith):
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return (f for f in self.extra_files if f.endswith(endswith))
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