whitequark e4d08d2855 back.pysim: delay clock processes by one half period. ... Makes it easier to see initial delta cycles.		2018-12-14 05:17:43 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	back.pysim: delay clock processes by one half period.	2018-12-14 05:17:43 +00:00
rtlil.py	fhdl.ir: move Fragment prepare logic from back.rtlil.	2018-12-13 14:34:07 +00:00
verilog.py	back.verilog: remove debug code.	2018-12-13 13:42:54 +00:00