whitequark e5e23644a4 hdl.{ast,dst}: directly represent RTLIL default case. ... This makes RTLIL mildly nicer: casez ({ \$5 , \$3 , \$1 }) 3'bzz1: \$next\o = \$7 ; 3'bz1z: \$next\o = \$9 ; 3'b1zz: \$next\o = \$11 ; - 3'bz: + default: { \$next\co , \$next\o } = \$13 ; endcase		2019-06-25 22:01:14 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.{ast,dst}: directly represent RTLIL default case.	2019-06-25 22:01:14 +00:00
rtlil.py	back.rtlil: mask memory init values.	2019-06-11 03:43:09 +00:00
verilog.py	back.verilog: allow stripping the src attribute, for cleaner output.	2019-04-22 14:59:53 +00:00