whitequark e5e23644a4 hdl.{ast,dst}: directly represent RTLIL default case. ... This makes RTLIL mildly nicer: casez ({ \$5 , \$3 , \$1 }) 3'bzz1: \$next\o = \$7 ; 3'bz1z: \$next\o = \$9 ; 3'b1zz: \$next\o = \$11 ; - 3'bz: + default: { \$next\co , \$next\o } = \$13 ; endcase		2019-06-25 22:01:14 +00:00
..
back	hdl.{ast,dst}: directly represent RTLIL default case.	2019-06-25 22:01:14 +00:00
build	build.plat: dedent overrides.	2019-06-16 12:40:52 +00:00
compat	compat.fhdl.structure: fix Case().makedefault().	2019-06-13 03:56:57 +00:00
hdl	hdl.{ast,dst}: directly represent RTLIL default case.	2019-06-25 22:01:14 +00:00
lib	lib.cdc: fix typo.	2019-06-09 10:24:01 +00:00
test	hdl.{ast,dst}: directly represent RTLIL default case.	2019-06-25 22:01:14 +00:00
vendor	vendor.xilinx_{spartan6,7series}: speedgrade→speed.	2019-06-25 15:51:52 +00:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	Clean up imports.	2019-06-04 08:18:50 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00