amaranth/nmigen
awygle ea94c9cc45
hdl.rec: proxy operators correctly.
Commit abbebf8e used __getattr__ to proxy Value methods called on 
Record. However, that did not proxy operators like __add__ because
Python looks up the special operator methods directly on the class
and does not run __getattr__ if they are missing.

Instead of using __getattr__, explicitly enumerate and wrap every
Value method that should be proxied. This also ensures backwards
compatibility if more methods are added to Value later.

Fixes #533.
2020-11-09 20:20:25 +00:00
..
_toolchain _toolchain.cxx: work around PyPy missing LDCXXSHARED sysconfig variable. 2020-08-27 06:53:14 +00:00
back back.{verilog,rtlil}: adjust $verilog_initial_trigger insertion. 2020-10-25 01:59:46 +00:00
build build.dsl: clean up inversion logic. 2020-10-26 19:50:21 +00:00
compat sim: split into base, core, and engines. 2020-08-27 11:52:31 +00:00
hdl hdl.rec: proxy operators correctly. 2020-11-09 20:20:25 +00:00
lib lib.fifo: fix {r,w}_level in AsyncFIFOBuffered 2020-11-03 09:34:12 +00:00
sim sim.pysim: avoid redundant VCD updates. 2020-11-06 02:05:35 +00:00
test tests: keep comments up to date. NFC. 2020-10-15 17:02:50 +00:00
vendor vendor.intel: add support for Cyclone V internal oscillator 2020-11-06 11:35:18 +00:00
__init__.py CI: fix code coverage collection. 2020-10-15 18:09:04 +00:00
_unused.py _unused: extract must-use logic from hdl.ir. 2020-02-01 01:35:05 +00:00
_utils.py hdl.ir: allow disabling UnusedElaboratable warning in file scope. 2019-10-26 06:17:14 +00:00
asserts.py hdl.ast,back.rtlil: implement Cover. 2019-09-03 01:32:24 +00:00
cli.py Fix commit 8313d6e7. 2020-11-06 01:54:30 +00:00
rpc.py rpc: add public Records as module ports. 2019-09-30 18:28:21 +00:00
tracer.py tracer: fix get_var_name() to work on toplevel attributes. 2020-05-17 19:51:58 +00:00
utils.py {,_}tools→{,_}utils 2019-10-13 18:53:38 +00:00