whitequark a7be3b480a hdl.ir: resolve hierarchy conflicts before creating missing domains. ... Otherwise, code such as: m.submodules.a = (something with cd_sync) m.submodules.b = (something with cd_sync) m.d.b_sync += x.eq(y) causes an assertion failure. Fixes #304 (again).		2020-01-18 10:30:36 +00:00
..
__init__.py	Remove everything deprecated in nmigen 0.1.	2020-01-12 13:59:26 +00:00
ast.py	Remove everything deprecated in nmigen 0.1.	2020-01-12 13:59:26 +00:00
cd.py	hdl.cd: add negedge clock domains.	2019-08-31 22:05:48 +00:00
dsl.py	{,_}tools→{,_}utils	2019-10-13 18:53:38 +00:00
ir.py	hdl.ir: resolve hierarchy conflicts before creating missing domains.	2020-01-18 10:30:36 +00:00
mem.py	hdl.mem: fix src_loc_at in ReadPort, WritePort.	2019-12-15 11:46:26 +00:00
rec.py	Remove everything deprecated in nmigen 0.1.	2020-01-12 13:59:26 +00:00
xfrm.py	hdl.xfrm: transform drivers as well in DomainRenamer.	2020-01-17 02:13:46 +00:00