whitequark eeb6aca93d compat.fhdl.specials: use "sync" as default domain, not "sys". ... In compat.fhdl.module, we already default to "sync" as the default clocked domain. Using "sys" in memories only would be inconsistent and result in more bugs.		2019-07-03 13:25:12 +00:00
..
back	back.rtlil: emit \sig$next wires instead of \$next\sig. NFC.	2019-07-02 18:06:50 +00:00
build	build.plat: add iter_extra_files method.	2019-07-02 18:25:29 +00:00
compat	compat.fhdl.specials: use "sync" as default domain, not "sys".	2019-07-03 13:25:12 +00:00
hdl	hdl.ast: recognize a Enum used as decoder and format it better.	2019-07-02 19:34:44 +00:00
lib	hdl.mem: use read_port(domain="comb") for asynchronous read ports.	2019-07-01 19:56:49 +00:00
test	hdl.ast: recognize a Enum used as decoder and format it better.	2019-07-02 19:34:44 +00:00
vendor	lattice_ecp5: fix get_input	2019-07-03 10:25:32 +08:00
__init__.py	Clean up imports.	2019-06-04 08:18:50 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	Clean up imports.	2019-06-04 08:18:50 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00