whitequark d47c1f8a8a back.rtlil: use one $meminit cell, not one per word. ... This is *far* more efficient.		2018-12-24 11:53:58 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.xfrm: Abstract*Transformer→*Visitor	2018-12-22 06:03:39 +00:00
rtlil.py	back.rtlil: use one $meminit cell, not one per word.	2018-12-24 11:53:58 +00:00
verilog.py	back.verilog: do not rename internal signals.	2018-12-22 00:53:40 +00:00