whitequark f417725b10 build.res: if not specified, request resource #0. ... This markedly differs from oMigen system, which would request consecutive resources. The difference is deliberate; most resources are singular, so it does not matter for them, and for resources where it does matter, which pins are requested should not depend on order of execution of `platform.request`.		2019-06-03 02:54:17 +00:00
..
back	back.rtlil: allow specifying platform for convert().	2019-05-26 17:10:56 +00:00
build	build.res: if not specified, request resource #0.	2019-06-03 02:54:17 +00:00
compat	Add import so that Tristate.elaborate builds	2019-05-20 16:34:31 +00:00
hdl	hdl.ir: accept LHS signals like slices as Instance io ports.	2019-06-03 02:39:14 +00:00
lib	lib.io: add a name argument to the Pin constructor.	2019-04-24 22:02:20 +00:00
test	vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras.	2019-06-03 02:51:59 +00:00
vendor	vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras.	2019-06-03 02:51:59 +00:00
__init__.py	Add versioneer.	2019-05-26 11:20:13 +00:00
_version.py	Add versioneer.	2019-05-26 11:20:13 +00:00
cli.py	hdl.ir: rename .get_fragment() to .elaborate().	2019-01-26 02:31:12 +00:00
formal.py	formal: extract from toplevel module.	2019-01-17 01:43:07 +00:00
tools.py	hdl: make all public Value classes other than Record final.	2019-05-12 05:40:17 +00:00
tracer.py	tracer: factor out get_var_name(default=).	2019-03-03 18:21:22 +00:00