| .. |
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back
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back.pysim: accept write_vcd(vcd_file=None).
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2020-02-12 14:42:06 +00:00 |
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build
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build.res,vendor: place clock constraint on port, not net, if possible.
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2020-02-06 23:37:15 +00:00 |
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compat
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_unused: extract must-use logic from hdl.ir.
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2020-02-01 01:35:05 +00:00 |
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hdl
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hdl.ast: add Value.{as_signed,as_unsigned}.
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2020-02-06 18:27:55 +00:00 |
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lib
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nmigen.lib.cdc: port PulseSynchronizer.
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2020-02-16 06:51:53 +00:00 |
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test
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nmigen.lib.cdc: port PulseSynchronizer.
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2020-02-16 06:51:53 +00:00 |
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vendor
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build.res,vendor: place clock constraint on port, not net, if possible.
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2020-02-06 23:37:15 +00:00 |
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__init__.py
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Remove everything deprecated in nmigen 0.1.
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2020-01-12 13:59:26 +00:00 |
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_toolchain.py
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Refactor build script toolchain lookups.
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2019-10-13 13:53:24 +00:00 |
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_unused.py
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_unused: extract must-use logic from hdl.ir.
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2020-02-01 01:35:05 +00:00 |
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_utils.py
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hdl.ir: allow disabling UnusedElaboratable warning in file scope.
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2019-10-26 06:17:14 +00:00 |
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asserts.py
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hdl.ast,back.rtlil: implement Cover.
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2019-09-03 01:32:24 +00:00 |
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cli.py
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cli: update use of deprecated code.
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2020-02-12 14:42:24 +00:00 |
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rpc.py
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rpc: add public Records as module ports.
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2019-09-30 18:28:21 +00:00 |
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tracer.py
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tracer: fix typo.
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2019-08-19 20:20:18 +00:00 |
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utils.py
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{,_}tools→{,_}utils
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2019-10-13 18:53:38 +00:00 |
