whitequark 59c7540aeb back.rtlil: split processes as finely as possible. ... This makes simulation work correctly (by introducing delta cycles, and therefore, making the overall Verilog simulation deterministic) at the price of pessimizing mux trees generated by Yosys and Synplify frontends, sometimes severely.		2018-12-22 10:03:16 +00:00
..
__init__.py	Initial commit.	2018-12-12 03:18:44 +00:00
pysim.py	hdl.xfrm: Abstract*Transformer→*Visitor	2018-12-22 06:03:39 +00:00
rtlil.py	back.rtlil: split processes as finely as possible.	2018-12-22 10:03:16 +00:00
verilog.py	back.verilog: do not rename internal signals.	2018-12-22 00:53:40 +00:00