2021-12-09 22:39:50 -07:00
|
|
|
from amaranth import *
|
2024-02-14 03:27:39 -07:00
|
|
|
from amaranth.lib.memory import Memory
|
2021-12-09 22:39:50 -07:00
|
|
|
from amaranth.cli import main
|
2018-12-20 18:55:59 -07:00
|
|
|
|
|
|
|
|
2019-04-21 02:52:57 -06:00
|
|
|
class RegisterFile(Elaboratable):
|
2018-12-20 18:55:59 -07:00
|
|
|
def __init__(self):
|
|
|
|
self.adr = Signal(4)
|
|
|
|
self.dat_r = Signal(8)
|
|
|
|
self.dat_w = Signal(8)
|
|
|
|
self.we = Signal()
|
2024-02-14 03:27:39 -07:00
|
|
|
self.mem = Memory(shape=8, depth=16, init=[0xaa, 0x55])
|
2018-12-20 18:55:59 -07:00
|
|
|
|
2019-01-25 19:31:12 -07:00
|
|
|
def elaborate(self, platform):
|
2018-12-20 18:55:59 -07:00
|
|
|
m = Module()
|
2024-02-14 03:27:39 -07:00
|
|
|
m.submodules.mem = self.mem
|
|
|
|
rdport = self.mem.read_port()
|
|
|
|
wrport = self.mem.write_port()
|
2018-12-20 18:55:59 -07:00
|
|
|
m.d.comb += [
|
|
|
|
rdport.addr.eq(self.adr),
|
|
|
|
self.dat_r.eq(rdport.data),
|
|
|
|
wrport.addr.eq(self.adr),
|
|
|
|
wrport.data.eq(self.dat_w),
|
|
|
|
wrport.en.eq(self.we),
|
|
|
|
]
|
2019-01-25 19:31:12 -07:00
|
|
|
return m
|
2018-12-20 18:55:59 -07:00
|
|
|
|
|
|
|
|
2018-12-22 16:56:02 -07:00
|
|
|
if __name__ == "__main__":
|
|
|
|
rf = RegisterFile()
|
|
|
|
main(rf, ports=[rf.adr, rf.dat_r, rf.dat_w, rf.we])
|