2018-12-15 07:20:10 -07:00
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from nmigen import *
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2019-09-06 00:47:27 -06:00
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from nmigen.lib.cdc import MultiReg
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2018-12-22 16:56:02 -07:00
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from nmigen.cli import main
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2018-12-12 03:12:35 -07:00
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i, o = Signal(name="i"), Signal(name="o")
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2018-12-13 04:35:20 -07:00
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m = Module()
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m.submodules += MultiReg(i, o)
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2018-12-22 16:56:02 -07:00
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if __name__ == "__main__":
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2019-01-26 09:25:05 -07:00
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main(m, ports=[i, o])
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