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amaranth/nmigen/sim/_pyclock.py

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sim._pyclock: new type of process. The overhead of coroutine processes is fairly high. A clock driver implemented through a coroutine process is mostly overhead. This was partially addressed in commit 2398b792 by microoptimizing yielding. This commit eliminates the coroutine process overhead completely by introducing dedicated clock processes. It also simplifies the logic to a simple toggle. This change improves runtime by about 12% on Minerva SRAM SoC.
2020-08-27 01:54:27 -06:00
import inspect
sim: split into base, core, and engines. Before this commit, each simulation engine (which is only pysim at the moment, but also cxxsim soon) was a subclass of SimulatorCore, and every simulation engine module would essentially duplicate the complete structure of a simulator, with code partially shared. This was a really bad idea: it was inconvenient to use, with downstream code having to branch between e.g. PySettle and CxxSettle; it had no well-defined external interface; it had multiple virtually identical entry points; and it had no separation between simulation algorithms and glue code. This commit completely rearranges simulation code. 1. sim._base defines internal simulation interfaces. The clarity of these internal interfaces is important because simulation engines mix and match components to provide a consistent API regardless of the chosen engine. 2. sim.core defines the external simulation interface: the commands and the simulator facade. The facade provides a single entry point and, when possible, validates or lowers user input. It also imports built-in simulation engines by their symbolic name, avoiding eager imports of pyvcd or ctypes. 3. sim.xxxsim (currently, only sim.pysim) defines the simulator implementation: time and state management, process scheduling, and waveform dumping. The new simulator structure has none of the downsides of the old one. See #324.
2020-08-27 04:17:02 -06:00
from ._base import BaseProcess
sim._pyclock: new type of process. The overhead of coroutine processes is fairly high. A clock driver implemented through a coroutine process is mostly overhead. This was partially addressed in commit 2398b792 by microoptimizing yielding. This commit eliminates the coroutine process overhead completely by introducing dedicated clock processes. It also simplifies the logic to a simple toggle. This change improves runtime by about 12% on Minerva SRAM SoC.
2020-08-27 01:54:27 -06:00
__all__ = ["PyClockProcess"]
sim: split into base, core, and engines. Before this commit, each simulation engine (which is only pysim at the moment, but also cxxsim soon) was a subclass of SimulatorCore, and every simulation engine module would essentially duplicate the complete structure of a simulator, with code partially shared. This was a really bad idea: it was inconvenient to use, with downstream code having to branch between e.g. PySettle and CxxSettle; it had no well-defined external interface; it had multiple virtually identical entry points; and it had no separation between simulation algorithms and glue code. This commit completely rearranges simulation code. 1. sim._base defines internal simulation interfaces. The clarity of these internal interfaces is important because simulation engines mix and match components to provide a consistent API regardless of the chosen engine. 2. sim.core defines the external simulation interface: the commands and the simulator facade. The facade provides a single entry point and, when possible, validates or lowers user input. It also imports built-in simulation engines by their symbolic name, avoiding eager imports of pyvcd or ctypes. 3. sim.xxxsim (currently, only sim.pysim) defines the simulator implementation: time and state management, process scheduling, and waveform dumping. The new simulator structure has none of the downsides of the old one. See #324.
2020-08-27 04:17:02 -06:00
class PyClockProcess(BaseProcess):
sim._pyclock: new type of process. The overhead of coroutine processes is fairly high. A clock driver implemented through a coroutine process is mostly overhead. This was partially addressed in commit 2398b792 by microoptimizing yielding. This commit eliminates the coroutine process overhead completely by introducing dedicated clock processes. It also simplifies the logic to a simple toggle. This change improves runtime by about 12% on Minerva SRAM SoC.
2020-08-27 01:54:27 -06:00
def __init__(self, state, signal, *, phase, period):
assert len(signal) == 1
self.state = state
self.slot = self.state.get_signal(signal)
self.phase = phase
self.period = period
self.reset()
def reset(self):
self.runnable = True
self.passive = True
sim: split into base, core, and engines. Before this commit, each simulation engine (which is only pysim at the moment, but also cxxsim soon) was a subclass of SimulatorCore, and every simulation engine module would essentially duplicate the complete structure of a simulator, with code partially shared. This was a really bad idea: it was inconvenient to use, with downstream code having to branch between e.g. PySettle and CxxSettle; it had no well-defined external interface; it had multiple virtually identical entry points; and it had no separation between simulation algorithms and glue code. This commit completely rearranges simulation code. 1. sim._base defines internal simulation interfaces. The clarity of these internal interfaces is important because simulation engines mix and match components to provide a consistent API regardless of the chosen engine. 2. sim.core defines the external simulation interface: the commands and the simulator facade. The facade provides a single entry point and, when possible, validates or lowers user input. It also imports built-in simulation engines by their symbolic name, avoiding eager imports of pyvcd or ctypes. 3. sim.xxxsim (currently, only sim.pysim) defines the simulator implementation: time and state management, process scheduling, and waveform dumping. The new simulator structure has none of the downsides of the old one. See #324.
2020-08-27 04:17:02 -06:00
sim._pyclock: new type of process. The overhead of coroutine processes is fairly high. A clock driver implemented through a coroutine process is mostly overhead. This was partially addressed in commit 2398b792 by microoptimizing yielding. This commit eliminates the coroutine process overhead completely by introducing dedicated clock processes. It also simplifies the logic to a simple toggle. This change improves runtime by about 12% on Minerva SRAM SoC.
2020-08-27 01:54:27 -06:00
self.initial = True
def run(self):
sim: split into base, core, and engines. Before this commit, each simulation engine (which is only pysim at the moment, but also cxxsim soon) was a subclass of SimulatorCore, and every simulation engine module would essentially duplicate the complete structure of a simulator, with code partially shared. This was a really bad idea: it was inconvenient to use, with downstream code having to branch between e.g. PySettle and CxxSettle; it had no well-defined external interface; it had multiple virtually identical entry points; and it had no separation between simulation algorithms and glue code. This commit completely rearranges simulation code. 1. sim._base defines internal simulation interfaces. The clarity of these internal interfaces is important because simulation engines mix and match components to provide a consistent API regardless of the chosen engine. 2. sim.core defines the external simulation interface: the commands and the simulator facade. The facade provides a single entry point and, when possible, validates or lowers user input. It also imports built-in simulation engines by their symbolic name, avoiding eager imports of pyvcd or ctypes. 3. sim.xxxsim (currently, only sim.pysim) defines the simulator implementation: time and state management, process scheduling, and waveform dumping. The new simulator structure has none of the downsides of the old one. See #324.
2020-08-27 04:17:02 -06:00
self.runnable = False
sim._pyclock: new type of process. The overhead of coroutine processes is fairly high. A clock driver implemented through a coroutine process is mostly overhead. This was partially addressed in commit 2398b792 by microoptimizing yielding. This commit eliminates the coroutine process overhead completely by introducing dedicated clock processes. It also simplifies the logic to a simple toggle. This change improves runtime by about 12% on Minerva SRAM SoC.
2020-08-27 01:54:27 -06:00
if self.initial:
self.initial = False
sim: split into base, core, and engines. Before this commit, each simulation engine (which is only pysim at the moment, but also cxxsim soon) was a subclass of SimulatorCore, and every simulation engine module would essentially duplicate the complete structure of a simulator, with code partially shared. This was a really bad idea: it was inconvenient to use, with downstream code having to branch between e.g. PySettle and CxxSettle; it had no well-defined external interface; it had multiple virtually identical entry points; and it had no separation between simulation algorithms and glue code. This commit completely rearranges simulation code. 1. sim._base defines internal simulation interfaces. The clarity of these internal interfaces is important because simulation engines mix and match components to provide a consistent API regardless of the chosen engine. 2. sim.core defines the external simulation interface: the commands and the simulator facade. The facade provides a single entry point and, when possible, validates or lowers user input. It also imports built-in simulation engines by their symbolic name, avoiding eager imports of pyvcd or ctypes. 3. sim.xxxsim (currently, only sim.pysim) defines the simulator implementation: time and state management, process scheduling, and waveform dumping. The new simulator structure has none of the downsides of the old one. See #324.
2020-08-27 04:17:02 -06:00
self.state.wait_interval(self, self.phase)
sim._pyclock: new type of process. The overhead of coroutine processes is fairly high. A clock driver implemented through a coroutine process is mostly overhead. This was partially addressed in commit 2398b792 by microoptimizing yielding. This commit eliminates the coroutine process overhead completely by introducing dedicated clock processes. It also simplifies the logic to a simple toggle. This change improves runtime by about 12% on Minerva SRAM SoC.
2020-08-27 01:54:27 -06:00
else:
clk_state = self.state.slots[self.slot]
clk_state.set(not clk_state.curr)
sim: split into base, core, and engines. Before this commit, each simulation engine (which is only pysim at the moment, but also cxxsim soon) was a subclass of SimulatorCore, and every simulation engine module would essentially duplicate the complete structure of a simulator, with code partially shared. This was a really bad idea: it was inconvenient to use, with downstream code having to branch between e.g. PySettle and CxxSettle; it had no well-defined external interface; it had multiple virtually identical entry points; and it had no separation between simulation algorithms and glue code. This commit completely rearranges simulation code. 1. sim._base defines internal simulation interfaces. The clarity of these internal interfaces is important because simulation engines mix and match components to provide a consistent API regardless of the chosen engine. 2. sim.core defines the external simulation interface: the commands and the simulator facade. The facade provides a single entry point and, when possible, validates or lowers user input. It also imports built-in simulation engines by their symbolic name, avoiding eager imports of pyvcd or ctypes. 3. sim.xxxsim (currently, only sim.pysim) defines the simulator implementation: time and state management, process scheduling, and waveform dumping. The new simulator structure has none of the downsides of the old one. See #324.
2020-08-27 04:17:02 -06:00
self.state.wait_interval(self, self.period / 2)
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