b65e11f38f
Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.
This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.
This commit completely rearranges simulation code.
1. sim._base defines internal simulation interfaces. The clarity of
these internal interfaces is important because simulation
engines mix and match components to provide a consistent API
regardless of the chosen engine.
2. sim.core defines the external simulation interface: the commands
and the simulator facade. The facade provides a single entry
point and, when possible, validates or lowers user input.
It also imports built-in simulation engines by their symbolic
name, avoiding eager imports of pyvcd or ctypes.
3. sim.xxxsim (currently, only sim.pysim) defines the simulator
implementation: time and state management, process scheduling,
and waveform dumping.
The new simulator structure has none of the downsides of the old one.
See #324.
37 lines
809 B
Python
37 lines
809 B
Python
import inspect
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from ._base import BaseProcess
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__all__ = ["PyClockProcess"]
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class PyClockProcess(BaseProcess):
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def __init__(self, state, signal, *, phase, period):
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assert len(signal) == 1
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self.state = state
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self.slot = self.state.get_signal(signal)
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self.phase = phase
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self.period = period
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self.reset()
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def reset(self):
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self.runnable = True
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self.passive = True
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self.initial = True
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def run(self):
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self.runnable = False
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if self.initial:
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self.initial = False
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self.state.wait_interval(self, self.phase)
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else:
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clk_state = self.state.slots[self.slot]
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clk_state.set(not clk_state.curr)
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self.state.wait_interval(self, self.period / 2)
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