2019-10-12 16:27:43 -06:00
|
|
|
from ..._tools import _ignore_deprecated
|
2018-12-18 11:05:37 -07:00
|
|
|
from ...compat import *
|
2019-01-26 08:29:09 -07:00
|
|
|
from ...compat.fhdl import verilog
|
2018-12-18 11:05:37 -07:00
|
|
|
|
|
|
|
|
|
|
|
class SimCase:
|
|
|
|
def setUp(self, *args, **kwargs):
|
2019-01-26 08:43:00 -07:00
|
|
|
with _ignore_deprecated():
|
|
|
|
self.tb = self.TestBench(*args, **kwargs)
|
2018-12-18 11:05:37 -07:00
|
|
|
|
2019-01-26 08:29:09 -07:00
|
|
|
def test_to_verilog(self):
|
|
|
|
verilog.convert(self.tb)
|
2018-12-18 11:05:37 -07:00
|
|
|
|
|
|
|
def run_with(self, generator):
|
2019-09-12 13:51:01 -06:00
|
|
|
with _ignore_deprecated():
|
|
|
|
run_simulation(self.tb, generator)
|