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hdl.mem: use 1 as reset value for ReadPort.en.

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This is necessary for consistency, since for transparent read ports,
we currently do not support .en at all (it is fixed at 1) due to
YosysHQ/yosys#760. Before this commit, changing port transparency
would require adding or removing an assignment to .en, which is
confusing and error-prone.

Also, most read ports are always enabled, so this behavior is also
convenient.
This commit is contained in:
whitequark 2019-09-20 19:36:19 +00:00
parent 91ef2f58e3
commit 4b3a068b15
3 changed files with 3 additions and 3 deletions
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2
nmigen/hdl/mem.py
View file

@ -88,7 +88,7 @@ class ReadPort(Elaboratable):
self.data = Signal(memory.width, self.data = Signal(memory.width,
name="{}_r_data".format(memory.name), src_loc_at=2) name="{}_r_data".format(memory.name), src_loc_at=2)
if self.domain != "comb" and not transparent: if self.domain != "comb" and not transparent:
self.en = Signal(name="{}_r_en".format(memory.name), src_loc_at=2) self.en = Signal(name="{}_r_en".format(memory.name), src_loc_at=2, reset=1)
else: else:
self.en = Const(1) self.en = Const(1)

1
nmigen/test/test_hdl_mem.py
View file

@ -60,6 +60,7 @@ class MemoryTestCase(FHDLTestCase):
self.assertEqual(rdport.transparent, False) self.assertEqual(rdport.transparent, False)
self.assertEqual(len(rdport.en), 1) self.assertEqual(len(rdport.en), 1)
self.assertIsInstance(rdport.en, Signal) self.assertIsInstance(rdport.en, Signal)
self.assertEqual(rdport.en.reset, 1)
def test_read_port_asynchronous(self): def test_read_port_asynchronous(self):
mem = Memory(width=8, depth=4) mem = Memory(width=8, depth=4)

3
nmigen/test/test_sim.py
View file

@ -548,9 +548,8 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
def process(): def process():
yield self.wrport.data.eq(0x33) yield self.wrport.data.eq(0x33)
yield self.wrport.en.eq(1) yield self.wrport.en.eq(1)
yield self.rdport.en.eq(1)
yield yield
self.assertEqual((yield self.rdport.data), 0x00) self.assertEqual((yield self.rdport.data), 0xaa)
yield yield
self.assertEqual((yield self.rdport.data), 0xaa) self.assertEqual((yield self.rdport.data), 0xaa)
yield Delay(1e-6) # let comb propagate yield Delay(1e-6) # let comb propagate