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build/plat: implement an override disabling debug Verilog generation.

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Currently debug Verilog generation can take many 10's of seconds.
A new override can now be passed as `AMARANTH_debug_verilog`=0 on
the environment or by setting the `debug_verilog` keyword argument
to `Platform.build()` or `Platform.prepare_toolchain()` to `False`.

Fixes #623.
This commit is contained in:
Irides 2022-04-05 15:43:30 -05:00 committed by Catherine
parent 9eb208c332
commit ee9da63287
1 changed files with 5 additions and 2 deletions
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7
amaranth/build/plat.py
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@ -367,8 +367,11 @@ class TemplatedPlatform(Platform):
strip_internal_attrs=True, write_verilog_opts=opts)
def emit_debug_verilog(opts=()):
return verilog._convert_rtlil_text(rtlil_text,
strip_internal_attrs=False, write_verilog_opts=opts)
if not get_override_flag("debug_verilog"):
return "/* Debug Verilog generation was disabled. */"
else:
return verilog._convert_rtlil_text(rtlil_text,
strip_internal_attrs=False, write_verilog_opts=opts)
def emit_commands(syntax):
commands = []