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Author SHA1 Message Date
whitequark 21379dd44b lib.cdc: eliminate no_retiming attributes. 
See #115 for rationale.
 2019-06-28 07:22:54 +00:00
whitequark 6454378fe7 vendor.lattice_ice40: fix instance of negedge FF due to a typo. 2019-06-28 07:05:20 +00:00
Alain Péteut 1609a5ba54 build.plat: fix dedent overrides. 2019-06-28 06:52:52 +00:00
whitequark f0a7f84a6d README: tone down the instability warning to reflect current status. 2019-06-28 05:10:29 +00:00
whitequark 32446831b4 hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values. 
This means that instead of:

    with m.Case(0b00):
        <body>
    with m.Case(0b01):
        <body>

it is legal to write:

    with m.Case(0b00, 0b01):
        <body>

with no change in semantics, and slightly nicer RTLIL or Verilog
output.

Fixes #103.
 2019-06-28 04:37:08 +00:00
whitequark 48d4ee4031 hdl.ir, back.rtlil: allow specifying attributes on instances. 
Fixes #107.
 2019-06-28 04:14:38 +00:00
whitequark 2b92f12016 examples: add concise UART example. 
This example uses shift registers and counters instead of an explicit
FSM, which makes it very compact in terms of generated logic, and
more concise too.
 2019-06-27 04:51:45 +00:00
whitequark 6f4e3156d8 back.pysim: fix scope screwup. 2019-06-26 05:22:09 +00:00
whitequark 2f7e52369c compat.fhdl.structure: fix typo. 2019-06-25 22:01:14 +00:00
whitequark b1af0601fa compat.fhdl.structure: simplify handling of default case. 2019-06-25 22:01:14 +00:00
whitequark e5e23644a4 hdl.{ast,dst}: directly represent RTLIL default case. 
This makes RTLIL mildly nicer:

 casez ({ \$5 , \$3 , \$1  })
   3'bzz1:
       \$next\o  = \$7 ;
   3'bz1z:
       \$next\o  = \$9 ;
   3'b1zz:
       \$next\o  = \$11 ;
-  3'bz:
+  default:
       { \$next\co , \$next\o  } = \$13 ;
 endcase
 2019-06-25 22:01:14 +00:00
whitequark f60ceb349b vendor.xilinx_{spartan6,7series}: speedgrade→speed. 
For consistency with ECP5.
 2019-06-25 15:51:52 +00:00
whitequark 0a145ed2d9 vendor.lattice_ecp5: implement. 
Note that because of issues with Yosys and nextpnr, it is not yet
possible to use either SDR or DDR I/O.
 2019-06-25 15:48:07 +00:00
Sebastien Bourdeauducq 56fe329e0c README: update nMigen libs paragraph 2019-06-24 10:05:25 +08:00
Sebastien Bourdeauducq 67c06b4540 README: add clarification about HLS 2019-06-24 10:00:31 +08:00
whitequark 23ed888857 vendor.lattice_ice40: use different --package for 4k devices. 2019-06-19 06:09:08 +00:00
Jean-François Nguyen b3c5ff7e95 vendor.xilinx_7series: fix IOB packing. 2019-06-17 20:48:46 +00:00
whitequark 3fc5f170e6 vendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explicitly. 
Do this to make sure all buffers, tristate/differential or not, are
instantiated the exact same way, and are subject to the same set of
toolchain bugs, if any.
 2019-06-17 15:47:56 +00:00
whitequark 2a8e7bc6f2 vendor.xilinx_{7series,spartan6}: cleanup. NFC. 
Eliminate some intermediate signals if they are not necessary.
Do not even return i, o, or t if the pin does not have them.
 2019-06-17 15:47:56 +00:00
whitequark 8b34602d91 vendor.xilinx_{7series,spartan6}: connect FCDE and IOB directly. 
Before this commit, in some cases there will be an inverter, which is
not allowed on an FDCE with IOB attribute set to true, as it will
interfere with packing.
 2019-06-17 15:47:56 +00:00
Alain Péteut 04c07715b4 build.plat: dedent overrides. 2019-06-16 12:40:52 +00:00
whitequark 70bbfecf6d vendor.lattice_ice40: never place an inverter on global buffer output. 
This would make `pin.i` not a global network anymore, which is likely
undesirable if an explicit Attrs(GLOBAL=1) is specified.
 2019-06-14 20:44:02 +00:00
Jean-François Nguyen 01a3101fd3 vendor.xilinx_7series: implement inverters. 2019-06-13 15:14:09 +00:00
Jean-François Nguyen 412781e0c3 vendor.xilinx_spartan6: implement DDR I/O buffers and inverters. 2019-06-13 15:13:31 +00:00
whitequark 2566747061 compat.fhdl.structure: fix Case().makedefault(). 
Fixes #100.
 2019-06-13 03:56:57 +00:00
whitequark f689b777b4 compat.fhdl.structure: always order default case as the very last. 2019-06-13 03:56:57 +00:00
whitequark f1174655b1 hdl.ast: tighten assertion in Switch(). 2019-06-13 03:56:57 +00:00
whitequark 6beba3a48b Simplify code by using Signal.like(name_suffix="..") appropriately. 2019-06-12 22:28:45 +00:00
whitequark e52b15d236 hdl.ast: add name_suffix=".." option to Signal.like(). 
This simplifies creation of related signals with nice names during
metaprogramming, e.g.

  def make_ff(m, sig):
      sig_ff = Signal.like(sig, name_suffix="_ff")
      m.d.sync += sig_ff.eq(sig)
      return sig_ff
 2019-06-12 22:26:57 +00:00
Jean-François Nguyen 3b303c3334 vendor.xilinx_7series: implement DDR I/O buffers. 2019-06-12 19:55:10 +00:00
whitequark d3ed390b9d vendor.lattice_ice40: fix typo. 2019-06-12 17:38:14 +00:00
whitequark efb2d773c3 build.{dsl,res,plat}: add PinsN and DiffPairsN. 2019-06-12 14:42:39 +00:00
whitequark ad1a40c934 hdl.ast: implement values with custom lowering. 2019-06-11 07:01:44 +00:00
whitequark 066dd799e8 back.pysim: check for a clock being added twice. 
This commit adds a best-effort error for a common mistake of adding
a clock driving the same domain twice, such as a result of
a copy-paste error.

Fixes #27.
 2019-06-11 03:54:22 +00:00
whitequark d2d8c2b8bf back.rtlil: mask memory init values. 
This handles both init values that are too wide, which happens if
their magnitude is too high, or if they're negative.

Fixes #96.
 2019-06-11 03:43:09 +00:00
whitequark 58e39f90ce hdl.mem: coerce memory init values to integers. 
The coercion is carefully chosen to accept (other than normal ints)
instances of e.g. np.int64, but reject instances of e.g. float.
See https://stackoverflow.com/a/48940855/254415 for details.

Fixes #93.
 2019-06-11 03:38:44 +00:00
Simon Kirkby 2423eabc15 lib.cdc: fix typo. 2019-06-09 10:24:01 +00:00
Jean-François Nguyen d5ba26b174 vendor.xilinx_spartan6: implement. 2019-06-07 08:58:41 +00:00
Jean-François Nguyen 2b3a0e9fa0 vendor.xilinx_7series: fix typos. 2019-06-07 07:33:20 +00:00
whitequark 12e8fe484d build.dsl: fix precondition check in Pins. 2019-06-06 20:40:49 +00:00
Jean-François Nguyen f26e612899 vendor.xilinx_7series: implement. 2019-06-06 13:22:15 +00:00
whitequark b45c5119f5 build.res: allow querying frequency of a previously constrained clock. 2019-06-05 12:51:53 +00:00
whitequark c9879c795b build.{dsl,res,plat}: apply clock constraints to signals, not resources. 
This adds the Clock() build DSL element, and adds a resource manager
function add_clock_constraint() that takes a Pin or a Signal.
Note that not all platforms, in particular not any nextpnr platforms
at the moment, can add constraints on arbitrary signals.

Fixes #86.
 2019-06-05 08:52:30 +00:00
whitequark ab3f103e5a build.dsl: replace extras= with Attrs(). 
This change proved more tricky than expected due to downstream
dependencies, so it also includes some secondary refactoring.
 2019-06-05 07:02:08 +00:00
whitequark c52cd72d3e Typos and style fixes. NFC. 2019-06-05 02:48:41 +00:00
whitequark 452c4b380b vendor.lattice_ice40: normalize device names. 
Right now the device name in the board file is just the option
nextpnr uses, but that's overnormalized and doesn't quite match
the chip names used elsewhere. It is even worse for ECP5 in terms
of mismatch with chip names, and for ECP5 we need to support other
toolchains as well, so let's handle this uniformly everywhere.
 2019-06-04 16:09:08 +00:00
whitequark 4379a5d6fe hdl.ir: rephrase elaboratable warning to not look like an error. 2019-06-04 13:11:15 +00:00
whitequark 537d91851d compat.fhdl.module: silence "unused elaboratable" warnings. 2019-06-04 13:09:36 +00:00
whitequark 38917e4523 compat.fhdl.specials: fix platform lowering for TSTriple again. 2019-06-04 13:03:56 +00:00
whitequark 79a3710255 compat.fhdl.specials: fix platform lowering. 
get_tristate only has O/OE; the triple is created by get_input_output.
 2019-06-04 12:26:09 +00:00