whitequark
53bb4300a3
build.plat: strip internal attributes from Verilog output.
...
Although useful for debugging, most external tools often complain
about such attributes (with notable exception of Vivado). As such,
it is better to emit Verilog with these attributes into a separate
file such as `design.debug.v` and only emit the attributes that were
explicitly placed by the user to `design.v`.
This still leaves the (*init*) attribute. See #220 for details.
2019-09-24 14:56:00 +00:00
Darrell Harmon
f3a8880cb8
vendor.xilinx_7series: apply false path / max delay constraints.
2019-09-24 00:47:54 +00:00
whitequark
59acd5d5a5
vendor.lattice_ice40: fix required tool list for iCECube2. NFC.
2019-09-22 07:18:37 +00:00
whitequark
3d62dac1cb
vendor.lattice_ice40: add iCECube support.
...
This also makes some iCE40 and ECP5 overrides more consistent.
2019-09-21 14:45:17 +00:00
whitequark
07a82ed70e
build.plat: NMIGEN_<toolchain>_env→NMIGEN_ENV_<toolchain>
...
This is more consistent with other environment variables nMigen uses.
2019-09-21 12:23:53 +00:00
whitequark
91ef2f58e3
vendor.lattice_{ecp5,ice40}: allow clock constraints on arbitrary signals.
...
Fixes #88 .
2019-09-20 16:26:27 +00:00
Emily
c4e8ac734f
_toolchain,build.plat,vendor.*: add required_tools list and checks.
2019-08-31 00:05:47 +00:00
whitequark
c77274c1ad
vendor: eliminate unnecessary LUT instantiation.
...
Fixes #165 .
2019-08-22 21:29:20 +00:00
whitequark
5889e62668
vendor.lattice_ice40: remove --placer heap default option.
...
It is not the place of nMigen to decide on this default, since both
SA and HeAP have valid uses that are not covered by the other.
2019-08-21 21:32:38 +00:00
whitequark
531040d2fd
vendor: style. NFC.
2019-08-21 21:32:36 +00:00
whitequark
77012fc143
vendor.lattice_ice40: use a local clock domain in create_missing_domain().
2019-08-19 21:46:44 +00:00
whitequark
1b379a513c
vendor.lattice_ice40: add iCE5LP2K support.
2019-08-07 09:25:20 +00:00
whitequark
cfbc678508
vendor.lattice_ice40: add iCE40UP3K support.
2019-08-07 09:06:27 +00:00
whitequark
9c35e44e4a
vendor.lattice_ice40: add iCE5LP1K support.
2019-08-07 09:01:11 +00:00
whitequark
27063a3bd3
vendor.xilinx_spartan_3_6: set bitgen defaults to -g Binary:Yes -g Compress.
...
* `-g Binary:Yes` should be overridable.
* `-g Compress` is a good default.
2019-08-04 14:18:49 +00:00
whitequark
34a97b2751
vendor.lattice_ice40: avoid routing conflicts with SDR/DDR input pins.
2019-08-04 00:30:50 +00:00
whitequark
999a2f612a
vendor.lattice_ice40: add missing signal indexing.
2019-08-03 22:59:33 +00:00
whitequark
8854ca03ae
build.plat,vendor: automatically create sync domain from default_clk.
...
But only if it is not defined by the programmer.
Closes #57 .
2019-08-03 18:36:58 +00:00
N. Engelhardt
5fd8a796ae
vendor: don't emit duplicate iobuf submodule names.
...
These are no longer allowed after commit 698b005
2019-07-21 07:49:21 +00:00
whitequark
146f3cb684
build.plat: source a script with toolchain environment.
...
Fixes #131 .
2019-07-07 00:44:28 +00:00
whitequark
1ee21d2007
build.plat, vendor.*: don't join strings passed as _opts overrides.
...
Right now an array is expected in any _opts overrides, and if it is
actually a string (because it is passed via an environment variable,
usually), awkwardness results as each character is joined with ` `.
Fixes #130 .
2019-07-06 23:09:46 +00:00
whitequark
33f21628bb
vendor: give names to IO buffer instances.
...
Fixes #123 .
2019-07-03 14:43:03 +00:00
Alain Péteut
20553b1478
build.plat: add iter_extra_files method.
...
* vendor.*: employ iter_extra_files.
2019-07-02 18:25:29 +00:00
whitequark
6454378fe7
vendor.lattice_ice40: fix instance of negedge FF due to a typo.
2019-06-28 07:05:20 +00:00
whitequark
23ed888857
vendor.lattice_ice40: use different --package for 4k devices.
2019-06-19 06:09:08 +00:00
whitequark
2a8e7bc6f2
vendor.xilinx_{7series,spartan6}: cleanup. NFC.
...
Eliminate some intermediate signals if they are not necessary.
Do not even return i, o, or t if the pin does not have them.
2019-06-17 15:47:56 +00:00
whitequark
70bbfecf6d
vendor.lattice_ice40: never place an inverter on global buffer output.
...
This would make `pin.i` not a global network anymore, which is likely
undesirable if an explicit Attrs(GLOBAL=1) is specified.
2019-06-14 20:44:02 +00:00
whitequark
6beba3a48b
Simplify code by using Signal.like(name_suffix="..") appropriately.
2019-06-12 22:28:45 +00:00
whitequark
d3ed390b9d
vendor.lattice_ice40: fix typo.
2019-06-12 17:38:14 +00:00
whitequark
efb2d773c3
build.{dsl,res,plat}: add PinsN and DiffPairsN.
2019-06-12 14:42:39 +00:00
whitequark
c9879c795b
build.{dsl,res,plat}: apply clock constraints to signals, not resources.
...
This adds the Clock() build DSL element, and adds a resource manager
function add_clock_constraint() that takes a Pin or a Signal.
Note that not all platforms, in particular not any nextpnr platforms
at the moment, can add constraints on arbitrary signals.
Fixes #86 .
2019-06-05 08:52:30 +00:00
whitequark
ab3f103e5a
build.dsl: replace extras= with Attrs().
...
This change proved more tricky than expected due to downstream
dependencies, so it also includes some secondary refactoring.
2019-06-05 07:02:08 +00:00
whitequark
c52cd72d3e
Typos and style fixes. NFC.
2019-06-05 02:48:41 +00:00
whitequark
452c4b380b
vendor.lattice_ice40: normalize device names.
...
Right now the device name in the board file is just the option
nextpnr uses, but that's overnormalized and doesn't quite match
the chip names used elsewhere. It is even worse for ECP5 in terms
of mismatch with chip names, and for ECP5 we need to support other
toolchains as well, so let's handle this uniformly everywhere.
2019-06-04 16:09:08 +00:00
whitequark
1b54eb80da
vendor.board: split off into nmigen-boards package.
...
The iCE40 programmers are also moved, since they're board-specific.
(It looks like iceprog isn't, but it only works with Lattice
evaluation kits.)
Fixes #80 .
2019-06-04 09:52:33 +00:00
