whitequark
eb04a2509e
hdl.mem,lib,examples: use Signal.range().
2019-09-08 12:19:13 +00:00
whitequark
5e9587bbbd
Remove nmigen.lib from prelude.
...
Currently it's just MultiReg, and there's no particularly good reason
to privilege this specific CDC primitive so much.
2019-09-06 06:53:06 +00:00
Reto Kramer
b0ef53e095
examples/basic/uart: document divisor parameter.
2019-08-22 19:28:40 +00:00
whitequark
fa0fa056ba
hdl.xfrm: CEInserter→EnableInserter.
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Fixes #166 .
2019-08-12 13:39:26 +00:00
whitequark
5c63177fc2
test: generate examples to verilog as part of unit tests.
...
This is to make sure 806a62c2 doesn't happen again.
2019-07-08 10:12:26 +00:00
whitequark
c14d074fcc
examples/basic/ctr_ce: fix outdated syntax.
2019-07-08 10:12:26 +00:00
whitequark
2b92f12016
examples: add concise UART example.
...
This example uses shift registers and counters instead of an explicit
FSM, which makes it very compact in terms of generated logic, and
more concise too.
2019-06-27 04:51:45 +00:00
whitequark
3d04122d55
examples: reorganize into examples/basic and examples/board.
2019-06-03 16:17:37 +00:00
