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Author SHA1 Message Date
whitequark 2e6627c4af back.rtlil: use a dummy wire, not 'x, when assigning to shorter LHS. 
Using 'x is legal RTLIL, in theory, but in practice it crashes Yosys
and when it doesn't, it causes Yosys to produce invalid Verilog.
Using a dummy wire is always safe and is not a major readability
issue as this is a rare corner case.

(It is not trivial to shorten the RHS in this case, because during
expansion of an ArrayProxy, match_shape() could be called in
a context far from the RHS handling logic.)
 2019-08-04 00:12:08 +00:00
whitequark d0ac8bf789 back.rtlil: actually match shape of left hand side. 
This comes up in code such as:
  Array([Signal(1), Signal(8)]).eq(Const(0, 8))
 2019-08-03 23:48:28 +00:00
whitequark 999a2f612a vendor.lattice_ice40: add missing signal indexing. 2019-08-03 22:59:33 +00:00
whitequark 8dd54ac544 build.run: use keyword-only arguments where appropriate. 2019-08-03 22:52:58 +00:00
whitequark 0fe05188e8 compat.fhdl.specials: track changes in build.plat. 2019-08-03 22:52:34 +00:00
whitequark 99d205494a hdl.dsl: reword m.If(~True) warning to be more clear. 
Before this commit, it only suggested one thing (silencing it) and
that's wrong almost all of the time, so suggest the right thing
instead.
 2019-08-03 18:52:24 +00:00
whitequark 8854ca03ae build.plat,vendor: automatically create sync domain from default_clk. 
But only if it is not defined by the programmer.

Closes #57.
 2019-08-03 18:36:58 +00:00
whitequark e0b54b417e hdl.ir: allow adding more than one domain in missing domain callback. 
This is useful for injecting complex power-on reset logic.
 2019-08-03 18:19:40 +00:00
whitequark 9c28b61d9f hdl.ir: don't expose as ports missing domains added via elaboratables. 
The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.
 2019-08-03 16:39:21 +00:00
whitequark 21f2f8c46e build.plat: add default_rst, to be used with default_clk. 2019-08-03 16:28:03 +00:00
whitequark 4dbb5352ad build.plat: add default_clk{,_constraint,_frequency}. 
This is the equivalent of oMigen's default_clk and default_clk_period
except the period is taken from the resource.
 2019-08-03 16:18:46 +00:00
whitequark cea92e9531 hdl.ir: allow returning elaboratables from missing domain callback. 
This allows e.g. injecting a clock/reset generator in platform build
code on demand (i.e. if the domain is not instantiated manually).

See #57.
 2019-08-03 15:44:02 +00:00
whitequark fc846532c7 hdl.ir: raise DomainError if a domain is used but not defined. 
Before this commit, a KeyError would be raised elsewhere in guts of
hdl.ir, which is not helpful.
 2019-08-03 15:31:24 +00:00
whitequark fdb0c5a6bc hdl.ir: call back from Fragment.prepare if a clock domain is missing. 
See #57.
 2019-08-03 14:54:20 +00:00
whitequark ace2b5ff0a hdl.dsl: warn on suspicious statements like m.If(~True):. 
This pattern usually produces an extremely hard to notice bug that
will usually break a design when it is triggered, but will also be
hidden unless the pathological value of a boolean switch is used.

Fixes #159.
 2019-08-03 14:00:29 +00:00
whitequark ab5426ce74 Improve test added in 29fee01f to not leak warnings. 2019-08-03 13:44:44 +00:00
whitequark ee03eab52f back.rtlil: fix sim-synth mismatch with assigns following switches. 
Closes #155.
 2019-08-03 13:27:47 +00:00
whitequark 0a603b3844 hdl.ast: fix typo. 2019-08-03 13:21:09 +00:00
whitequark 94e13effad hdl.ast: deprecate Value.part, add Value.{bit,word}_select. 
Fixes #148.
 2019-08-03 13:07:06 +00:00
whitequark bcdc280a87 hdl.ast, back.rtlil: add source locations to anonymous wires. 
This might help with propagation of locations through optimizer
passes, since not all of them take care to preserve cells at all,
but usually wires stay intact when possible.

Also fixes incorrect source location on value.part().
 2019-08-03 12:51:57 +00:00
whitequark 29fee01f86 hdl.ir: warn if .elaborate() returns None. 
Fixes #164.
 2019-08-03 12:30:39 +00:00
whitequark 995e4adb8c hdl.xfrm: handle mem.{Read,Write}Port in CEInserter. 
Fixes #154.
 2019-07-31 05:20:05 +00:00
N. Engelhardt 5fd8a796ae vendor: don't emit duplicate iobuf submodule names. 
These are no longer allowed after commit 698b005.
 2019-07-21 07:49:21 +00:00
N. Engelhardt 698b005182 hdl.dsl: add getters to m.submodules. 2019-07-19 12:39:47 +00:00
Alain Péteut 81e59832fb lib.fifo: fix typo. 2019-07-15 14:12:33 +00:00
Staf Verhaegen ff343d5cf0 Pin: Add extra hierarchy level for name derivation 2019-07-14 19:30:12 +00:00
William D. Jones b963449b41 build.run: Ensure batch script returns proper error code. 2019-07-14 17:43:33 +00:00
whitequark ee15538cf0 back.pysim: correctly add gtkwave traces for signals with decoders. 2019-07-12 13:35:44 +00:00
William D. Jones 6ee760e83f build.dsl: Add optional name_suffix to Resource.family. 2019-07-10 15:41:23 +00:00
whitequark 278b624c66 back.pysim: avoid malformed VCD files when a decoder uses tabs. 2019-07-10 12:54:59 +00:00
whitequark 2fa858b003 hdl.ir: make UnusedElaboratable a real warning. 
Before this commit, it was a print statement, and therefore, command
interpreter options like -Wignore did not affect it. There is no API
to access the warning filter list, so it was turned into a real
warning; and further, since Python 3.6, tracemalloc can be used
as a standard method to display traceback to allocation site instead
of the ad-hoc traceback logic that was used in Elaboratable before.
 2019-07-10 12:46:54 +00:00
whitequark 37f363e338 back.rtlil: add decodings to cases when switching on a signal. 
Fixes #134.
 2019-07-09 19:48:15 +00:00
whitequark 10e56c75fb back.verilog: run proc_prune for much cleaner output. 
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@44bcb7a1.
 2019-07-09 19:28:09 +00:00
whitequark 00c5209a47 hdl.{ast,dsl},back.rtlil: track source locations for switch cases. 
This is a very new Yosys feature, and will require a Yosys build
newer than YosysHQ/yosys@93bc5aff.
 2019-07-09 19:26:47 +00:00
Jacob Lifshay 62b3e36612 tracer: add PyPy support to get_var_name(). 
Fixes #141.
 2019-07-09 07:29:01 +00:00
whitequark 367ad5aee7 build.dsl: add Resource.family abstraction. 2019-07-09 02:44:03 +00:00
whitequark 7b4fbf8e01 build.{dsl,res}: allow platform-dependent attributes using callables. 
Fixes #132.
 2019-07-08 11:15:04 +00:00
whitequark 0ab0a74ec1 hdl.rec: respect modifications to signals in Record.like(). 
Fixes #126.
 2019-07-08 10:59:15 +00:00
whitequark bfbeca4584 back.rtlil: don't name-prefix signals connected to instance ports. 
This gives particularly pathological results on IO buffers, like:
  connect \D_OUT_0 \user_led_0_user_led_0__o

Since subfragment signals are name-prefixed because this works well
for signals propagated upwards across hierarchy, this is never
desirable for instances.
 2019-07-08 10:48:07 +00:00
whitequark 0b844da4cf build.{dsl,res}: allow removing attributes from subsignals. 
This is useful when most attributes in a large composite resource
are the same, but a few signals are different, and also when building
abstractions around resources.

Fixes #128.
 2019-07-08 10:42:10 +00:00
whitequark f0c1c2cfeb build.dsl: allow assertions on subsignal widths. 
This is useful when building abstractions around resources where
the pin names are user-specified.

Fixes #129.
 2019-07-08 10:42:06 +00:00
whitequark a7fbff94d8 hdl.{ast,cd,dsl,xfrm}: reject inappropriately used comb domain. 
Fixes #125.
 2019-07-08 10:26:49 +00:00
whitequark 345a26b04b test: fix Travis. 2019-07-08 10:22:47 +00:00
whitequark 5c63177fc2 test: generate examples to verilog as part of unit tests. 
This is to make sure 806a62c2 doesn't happen again.
 2019-07-08 10:12:26 +00:00
whitequark c14d074fcc examples/basic/ctr_ce: fix outdated syntax. 2019-07-08 10:12:26 +00:00
whitequark 447bfa6ad5 compat.genlib.fsm: fix after commit dac62754. 2019-07-08 10:12:26 +00:00
whitequark ec7fcd3697 hdl.xfrm: don't overwrite source locations on ClockDomain signals. 
On the sample of examples/basic/*.py, there are no remaining
incorrectly inferred locations.
 2019-07-08 09:58:12 +00:00
whitequark 8c9fdf907f hdl.{dsl,mem,xfrm}: inject appropriate source locations. 
This primarily fixes the problem with source location precision in
Module (which used to trace locations from __exit__ of the context
managers, by which point everything interesting has been lost), but
also improves memory port and control inserter source locations.

On the sample of examples/basic/*.py, the only incorrectly inferred
remaining location is clk pointing to hdl/mem.py:166.
 2019-07-08 09:58:12 +00:00
whitequark 710a8d0bc1 back.rtlil: ignore empty source locations. 
This was a bug introduced during refactoring in 2492f490.
 2019-07-08 09:58:12 +00:00
whitequark dac6275493 hdl.ast: use keyword-only arguments as appropriate. 
As a motivation/related refactor, make sure each AST node exposes
src_loc_at in the constructor.
 2019-07-08 09:58:12 +00:00