5 commits

Author	SHA1	Message	Date
whitequark	3327deae92	vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files.	2019-06-03 03:01:56 +00:00
whitequark	dc17d06fe9	vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras. ... The PULLUP and PULLUP_RESISTOR extras are representable in the PCF file. The IO_STANDARD extra, however, can only be an SB_IO parameter.	2019-06-03 02:51:59 +00:00
whitequark	e4ebe03115	vendor.fpga.lattice_ice40: use .bin suffix for bitstream tempfiles.	2019-06-02 04:12:50 +00:00
Simon Kirkby	358b98e5de	vendor.tinyfpga_b: implement.	2019-06-02 01:20:09 +00:00
whitequark	321d245e95	vendor.fpga.lattice_ice40: implement.	2019-06-01 16:47:01 +00:00