whitequark
4948162f33
hdl.ir: rename .get_fragment() to .elaborate().
...
Closes #9 .
2019-01-26 02:31:12 +00:00
whitequark
7b25665fde
back.pysim: fix behavior of initial cycle for sync processes.
...
The current behavior was introduced in 6570271912e04e4e657027191782b841
2019-01-25 20:37:56 +00:00
whitequark
12e04e4ee5
back.pysim: wake up processes before ever committing any values.
...
Otherwise, the contract of the simulator to sync processes is not
always fulfilled.
2019-01-21 16:00:25 +00:00
whitequark
198efcad31
hdl.xfrm: add SampleLowerer.
2019-01-17 01:41:02 +00:00
William D. Jones
77728c2dea
hdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children.
2019-01-15 22:52:45 +00:00
whitequark
cbf7bd6e31
back.pysim: handle non-driven, non-port signals.
...
Fixes #20 .
2019-01-13 08:31:38 +00:00
Adam Greig
560bb007cc
Give the top level scope a name to fix VCD hierarchy.
2019-01-06 00:10:37 +00:00
William D. Jones
f77dc40256
hdl.xfrm: Add Assert and Assume abstract methods for StatementVisitor, implement for children.
2019-01-02 11:17:39 +00:00
whitequark
849c649259
back.pysim: warn if simulation is not run.
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This would have prevented 3ea35b85
2018-12-29 15:02:04 +00:00
whitequark
92a96e1644
hdl.rec: add basic record support.
2018-12-28 13:22:10 +00:00
whitequark
fe8cb55204
lib.cdc: add tests for MultiReg.
2018-12-26 12:58:30 +00:00
whitequark
98a9744be4
hdl.xfrm: Abstract*Transformer→*Visitor
2018-12-22 06:03:39 +00:00
whitequark
48d13e47ec
back.pysim: handle out of bounds ArrayProxy indexes.
2018-12-21 12:32:08 +00:00
whitequark
7ae7683fed
back.pysim: give numeric names to unnamed subfragments in VCD.
2018-12-21 12:29:33 +00:00
whitequark
a40e2cac4b
back.pysim: fix an issue with too few funclet slots.
2018-12-21 10:25:28 +00:00
whitequark
dbbcc49a71
hdl.ast: Cat.{operands→parts}
2018-12-18 19:15:50 +00:00
whitequark
4199674edd
back.pysim: implement *.
2018-12-18 18:02:21 +00:00
whitequark
07e9cfa939
test.sim: add tests for sync functionality and errors.
2018-12-18 17:53:50 +00:00
whitequark
7fa82a70be
back.pysim: eliminate most dictionary lookups.
...
This makes the Glasgow testsuite about 30% faster.
2018-12-18 16:36:54 +00:00
whitequark
c5f169988b
back.pysim: use arrays instead of dicts for signal values.
...
This makes the Glasgow testsuite about 40% faster.
2018-12-18 05:20:20 +00:00
whitequark
39605ef551
back.pysim: naming. NFC.
2018-12-18 04:46:36 +00:00
whitequark
65702719e8
back.pysim: fix an off-by-1 in add_sync_process().
2018-12-18 04:43:04 +00:00
whitequark
34b81d0b87
back.pysim: trigger processes waiting on Tick() exactly at clock edge.
2018-12-18 04:37:39 +00:00
whitequark
d6e98fd934
back.pysim: continue running simulator processes until they suspend.
2018-12-18 03:05:16 +00:00
whitequark
8d1639a5a8
hdl, back: add and use SignalSet/SignalDict.
2018-12-17 17:21:29 +00:00
whitequark
2be76fda3c
hdl.xfrm: separate AST traversal from AST identity mapping.
...
This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.
2018-12-16 11:25:52 +00:00
whitequark
d4e8d3e95a
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
2018-12-16 10:31:42 +00:00
whitequark
bdb8db2826
back.pysim: add (stub) LHSValueCompiler.
2018-12-15 21:01:38 +00:00
whitequark
20a04bca88
back.pysim: implement Part.
2018-12-15 20:58:06 +00:00
whitequark
54fb999c99
back.pysim: implement ArrayProxy.
2018-12-15 19:37:36 +00:00
whitequark
790eb05a92
Rename fhdl→hdl, genlib→lib.
2018-12-15 14:25:31 +00:00
whitequark
db4600d52b
fhdl.ast, back.pysim: implement shifts.
2018-12-15 09:58:30 +00:00
whitequark
3a8685c352
Consistently use '{!r}' in and only in TypeError messages.
2018-12-15 09:31:58 +00:00
whitequark
7108111ad0
back.pysim: preserve process locations through add_sync_process().
2018-12-14 23:27:36 +00:00
whitequark
0015713bfb
back.pysim: count delta cycles separately to avoid clock drift.
2018-12-14 20:52:41 +00:00
whitequark
a6a8703a0e
back.pysim: simplify.
2018-12-14 20:45:45 +00:00
whitequark
7e3cf26cf8
back.pysim: revert 70ebc6f2.
2018-12-14 19:46:08 +00:00
whitequark
71304c9fe7
back.pysim: fix implicit boolean conversion.
2018-12-14 19:08:06 +00:00
whitequark
fe5fb34fae
back.pysim: squash one level of hierarchy.
...
There's really no point in the "top" node.
2018-12-14 18:53:21 +00:00
whitequark
70ebc6f2c1
back.pysim: implement blocking assignment semantics correctly.
2018-12-14 18:47:12 +00:00
whitequark
120d817123
back.pysim: undriven sync signals should return to previous value.
2018-12-14 17:25:48 +00:00
whitequark
4f5b4a9bf4
back.pysim: in simulator sync processes, start by waiting for a tick.
...
This matches Migen behavior and also makes more sense.
2018-12-14 17:05:11 +00:00
whitequark
e230383aac
back.pysim: make initial phase configurable.
2018-12-14 16:46:16 +00:00
whitequark
88970ee29f
pysim.back: fix add_sync_process wrapper to handle signals correctly.
2018-12-14 16:21:53 +00:00
whitequark
9307a31678
back.pysim: Simulator({gtkw_signals→traces}=).
2018-12-14 15:23:22 +00:00
whitequark
e3f32a1faf
back.pysim: better naming. NFC.
2018-12-14 15:21:13 +00:00
whitequark
474d46ced8
back.pysim: implement most operators and add tests.
2018-12-14 14:21:22 +00:00
whitequark
d9aaf0114b
back.pysim: close .vcd/.gtkw files on context manager exit.
2018-12-14 13:59:03 +00:00
whitequark
1655b59d1b
back.pysim: show more legible names for processes in errors.
2018-12-14 13:50:19 +00:00
whitequark
625c55a3b8
back.pysim: throw exceptions back at processes.
2018-12-14 13:43:25 +00:00
