amaranth

Author	SHA1	Message	Date
whitequark	4948162f33	hdl.ir: rename .get_fragment() to .elaborate(). Closes #9.	2019-01-26 02:31:12 +00:00
whitequark	8c96675580	hdl.ast: add Past, Stable, Rose, Fell.	2019-01-17 04:31:27 +00:00
whitequark	b534e92dd5	hdl.ir: allow explicitly requesting flattening.	2019-01-14 17:04:23 +00:00
whitequark	040811c2e5	hdl.ir: add an API for retrieving generated values, like FSM signal. This is useful for tests.	2018-12-26 12:35:35 +00:00
whitequark	68dae9f50e	hdl.ir: flatten hierarchy based on memory accesses, too.	2018-12-22 21:43:46 +00:00
whitequark	fd89d2fc9d	hdl.ir: factor out _merge_subfragment. NFC.	2018-12-22 19:04:49 +00:00
whitequark	f6772759c8	hdl.ir: fix port propagation between siblings, in the other direction.	2018-12-22 00:31:31 +00:00
whitequark	913339c04a	hdl.ir: fix port propagation between siblings.	2018-12-21 23:53:18 +00:00
whitequark	fc7da1be2d	hdl.ir: do not flatten instances or collect ports from their statements. This results in absurd behavior for memories.	2018-12-21 13:52:18 +00:00
whitequark	b0bd7bfaca	hdl.ir: correctly handle named output and inout ports.	2018-12-21 04:03:03 +00:00
whitequark	f7fec804ec	ir: allow non-Signals in Instance ports.	2018-12-20 23:40:40 +00:00
whitequark	c7f9386eab	fhdl.ir: add black-box fragments, fragment parameters, and Instance.	2018-12-17 22:55:39 +00:00
whitequark	8d1639a5a8	hdl, back: add and use SignalSet/SignalDict.	2018-12-17 17:21:29 +00:00
whitequark	015998eba9	hdl.dsl: add clock domain support.	2018-12-16 23:51:24 +00:00
whitequark	790eb05a92	Rename fhdl→hdl, genlib→lib.	2018-12-15 14:25:31 +00:00

15 commits