whitequark
4948162f33
hdl.ir: rename .get_fragment() to .elaborate().
...
Closes #9 .
2019-01-26 02:31:12 +00:00
whitequark
7b25665fde
back.pysim: fix behavior of initial cycle for sync processes.
...
The current behavior was introduced in 6570271912e04e4e657027191782b841
2019-01-25 20:37:56 +00:00
whitequark
12e04e4ee5
back.pysim: wake up processes before ever committing any values.
...
Otherwise, the contract of the simulator to sync processes is not
always fulfilled.
2019-01-21 16:00:25 +00:00
whitequark
8c96675580
hdl.ast: add Past, Stable, Rose, Fell.
2019-01-17 04:31:27 +00:00
whitequark
cbf7bd6e31
back.pysim: handle non-driven, non-port signals.
...
Fixes #20 .
2019-01-13 08:31:38 +00:00
whitequark
849c649259
back.pysim: warn if simulation is not run.
...
This would have prevented 3ea35b85
2018-12-29 15:02:04 +00:00
whitequark
92a96e1644
hdl.rec: add basic record support.
2018-12-28 13:22:10 +00:00
whitequark
fa2af27bb0
hdl.mem: ensure transparent read port model has correct latency.
2018-12-21 13:01:08 +00:00
whitequark
48d13e47ec
back.pysim: handle out of bounds ArrayProxy indexes.
2018-12-21 12:32:08 +00:00
whitequark
e58d9ec74d
hdl.mem: add simulation model for memory.
2018-12-21 11:54:32 +00:00
whitequark
4199674edd
back.pysim: implement *.
2018-12-18 18:02:21 +00:00
whitequark
07e9cfa939
test.sim: add tests for sync functionality and errors.
2018-12-18 17:53:50 +00:00
whitequark
d4e8d3e95a
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
2018-12-16 10:31:42 +00:00
whitequark
d9579219ee
test.sim: generalize assertOperator. NFC.
2018-12-15 21:08:29 +00:00
whitequark
20a04bca88
back.pysim: implement Part.
2018-12-15 20:58:06 +00:00
whitequark
54fb999c99
back.pysim: implement ArrayProxy.
2018-12-15 19:37:36 +00:00
whitequark
790eb05a92
Rename fhdl→hdl, genlib→lib.
2018-12-15 14:25:31 +00:00
whitequark
b70340c0da
pyback.sim: test Slice, Cat, Repl.
2018-12-15 10:09:14 +00:00
whitequark
db4600d52b
fhdl.ast, back.pysim: implement shifts.
2018-12-15 09:58:30 +00:00
whitequark
579feaba4e
fhdl.ir: Fragment.{drive→add_driver}
2018-12-14 20:58:29 +00:00
whitequark
9307a31678
back.pysim: Simulator({gtkw_signals→traces}=).
2018-12-14 15:23:22 +00:00
whitequark
474d46ced8
back.pysim: implement most operators and add tests.
2018-12-14 14:21:22 +00:00
