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Author SHA1 Message Date
Alain Péteut
d69a4e29a8 examples.por: fix typo 2019-03-12 02:14:21 +00:00
whitequark
4027317835 lib.fifo: register GrayEncoder output before CDC. 
Without this register, static hazards in the encoder could cause
multiple encoder output bits to toggle, which would be incorrectly
sampled by the 2FF synchronizer.

Reported by @Wren6991.
 2019-03-03 18:23:51 +00:00
whitequark
e93bf4bf4b tracer: factor out get_var_name(default=). 2019-03-03 18:21:22 +00:00
whitequark
cac4b10b82 hdl.rec: remove __slots__. 
Left in by mistake.
 2019-03-03 18:21:22 +00:00
Alain Péteut
342bdbe75a setup.py: constrain Python version 
Installation should be constraint to supported Python versions, using `python_requires`,
refer to [1] for details.

[1] https://packaging.python.org/guides/distributing-packages-using-setuptools/#python-requires
 2019-02-22 08:45:28 +00:00
whitequark
8ee6bd80ff hdl.ir: raise a more descriptive error on non-elaboratable object. 2019-02-14 20:52:42 +00:00
whitequark
43e4833ddb back.rtlil: accept ast.Const as cell parameter. 2019-01-26 23:25:54 +00:00
whitequark
bc5a127fd2 hdl.ast: fix ValueKey for Cat. 2019-01-26 23:25:34 +00:00
whitequark
e844b0e095 compat.fhdl.module: fix typo. 2019-01-26 23:08:55 +00:00
whitequark
ce7ba70462 compat.fhdl.specials: fix __all__ list. 2019-01-26 22:59:33 +00:00
whitequark
6cd9f7db19 compat.genlib.resetsync: add shim for AsyncResetSynchronizer. 2019-01-26 18:24:36 +00:00
whitequark
2fb85a6170 compat.fifo: fix _FIFOInterface deprecation wrapper. 2019-01-26 18:23:58 +00:00
whitequark
f44ca291c1 lib.cdc: add ResetSynchronizer. 2019-01-26 18:07:59 +00:00
whitequark
e74dbc3377 back.pysim: support async reset. 2019-01-26 18:07:43 +00:00
whitequark
8686e9aa06 back.pysim: give better names to unnamed fragments and their signals. 
Was: top.#0, top.None_clk
Now: top.U0, top.U0_clk

(U for Unnamed, or similarly, an unit refdes.)
 2019-01-26 18:07:16 +00:00
whitequark
7acea8f3ce examples: update for newer API. 2019-01-26 16:25:05 +00:00
whitequark
b133eb735f back.rtlil: accept any elaboratable, not just fragments. 2019-01-26 16:11:29 +00:00
whitequark
4bf80a6e33 compat: suppress deprecation warnings that are internal or during test. 2019-01-26 15:43:00 +00:00
whitequark
7890c0adc8 test.compat: reenable tests converting to Verilog. 2019-01-26 15:29:09 +00:00
whitequark
4887771e4a compat.sim: fix deprecated stdlib import. 2019-01-26 15:26:54 +00:00
whitequark
4948162f33 hdl.ir: rename .get_fragment() to .elaborate(). 
Closes #9.
 2019-01-26 02:31:12 +00:00
whitequark
4922a73c5d test.compat: import tests from Migen as appropriate. 
test_signed and test_coding are adjusted slightly to account for
differences in comb propagation between the simulators; we might want
to revert that eventually.
 2019-01-26 01:01:03 +00:00
whitequark
f71e0fffbb hdl.ast: fix shape calculation for *. 
This was carried over from Migen, and is wrong there too.
Counterexample: 1'sd-1 * 4'sd-4 = 4'sd-4 (but should be 5'sd4).
 2019-01-26 00:56:40 +00:00
whitequark
7b25665fde back.pysim: fix behavior of initial cycle for sync processes. 
The current behavior was introduced in 65702719, which was a wrong
fix for an issue that was actually fixed in 12e04e4e. This commit
effectively reverts 65702719 and 1782b841.
 2019-01-25 20:37:56 +00:00
whitequark
1782b841b2 lib.fifo: in FIFOInterface.read(), check readable on the right cycle. 2019-01-22 07:03:46 +00:00
whitequark
eeb023a7f5 compat.genlib.fifo: adjust _FIFOInterface shim to not require fwft=. 2019-01-22 06:56:46 +00:00
whitequark
2c80f35de4 lib.fifo: fix typo in AsyncFIFO documentation. 2019-01-22 05:47:50 +00:00
whitequark
e33580cf4c lib.fifo: add AsyncFIFO and AsyncFIFOBuffered. 2019-01-21 16:02:46 +00:00
whitequark
12e04e4ee5 back.pysim: wake up processes before ever committing any values. 
Otherwise, the contract of the simulator to sync processes is not
always fulfilled.
 2019-01-21 16:00:25 +00:00
whitequark
52a9f818f1 compat.genlib.cdc: add missing import. 2019-01-20 03:03:56 +00:00
whitequark
c110fe6a9d compat.genlib.cdc: add GrayCounter and GrayDecoder shims. 2019-01-20 02:29:08 +00:00
whitequark
b6cff2c098 lib.coding: add GrayEncoder and GrayDecoder. 
Unlike the Migen ones, these are purely combinatorial.
 2019-01-20 02:20:34 +00:00
whitequark
9757157fe2 lib.coding: add width as attribute to all coders. 2019-01-20 01:59:09 +00:00
whitequark
9de9272709 lib.fifo: use memory in the FIFO model. 
This is unfortunately more complicated, but results in a much faster
proof.
 2019-01-19 09:27:56 +00:00
whitequark
6ea0a12dd4 lib.fifo: use model equivalence to simplify formal specification. 
This is unfortunately slow, and should probably be using theory
of arrays.
 2019-01-19 09:27:56 +00:00
whitequark
38b3c4af31 hdl.ast: implement shape for modulo operator. 2019-01-19 09:27:56 +00:00
whitequark
5e2b46f727 hdl.ast: add Value.implies. 2019-01-19 08:56:44 +00:00
whitequark
c5d67b0461 hdl.xfrm: mark internal registers used in lowering Sample(). 2019-01-19 07:27:32 +00:00
whitequark
94b23dd2c8 doc: update COMPAT_SUMMARY. 2019-01-19 02:20:40 +00:00
whitequark
e3b5b2acc8 fhdl.specials: add compatibility shim for Tristate. 2019-01-19 02:20:40 +00:00
whitequark
3ed519383c lib.fifo: fix simulation read/write methods to take only one cycle. 2019-01-19 01:38:09 +00:00
whitequark
45088f7824 compat.genlib.fifo: add aliases for SyncFIFO, SyncFIFOBuffered. 2019-01-19 01:06:51 +00:00
whitequark
97b990272e lib.fifo: formally verify FIFO contract. 2019-01-19 00:52:56 +00:00
whitequark
b50b47d984 hdl.ast: give Assert and Assume their own src_loc. 
This helps with patterns like `Assert(fsm.ongoing("IDLE"))`, which
would otherwise point into nMigen internals.
 2019-01-19 00:08:51 +00:00
whitequark
66466a8a0e back.rtlil: only emit each AnyConst/AnySeq cell once. 
These are semantically like signals, not like constants.
 2019-01-18 01:34:48 +00:00
Alain Péteut
60089db075 cli: add missing default for generate 2019-01-17 20:45:07 +00:00
whitequark
5a831ce31c lib.fifo: add basic formal specification. 2019-01-17 05:40:25 +00:00
whitequark
fa8e876356 hdl.ast: allow sampling ClockSignal, ResetSignal. 2019-01-17 05:23:06 +00:00
whitequark
8c96675580 hdl.ast: add Past, Stable, Rose, Fell. 2019-01-17 04:31:27 +00:00
whitequark
16f90d3585 formal: extract from toplevel module. 
The nMigen formal language is about to get *much* larger and will
keep growing faster than the rest of nMigen language, so it makes
good sense to extract it. Further, this makes it easier to qualify
formal keywords like `formal.AnyConst()` without directly importing
hdl.ast.
 2019-01-17 01:43:07 +00:00