whitequark
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6ee80408bb
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back.verilog: do not rename internal signals.
_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.
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2018-12-22 00:53:40 +00:00 |
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whitequark
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5361b4c22b
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compat: fix confusing naming for memory port address signal.
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2018-12-22 00:53:05 +00:00 |
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whitequark
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f6772759c8
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hdl.ir: fix port propagation between siblings, in the other direction.
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2018-12-22 00:31:31 +00:00 |
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whitequark
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0df543b204
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compat: do not finalize native submodules twice.
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2018-12-22 00:02:31 +00:00 |
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whitequark
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a4183eba69
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hdl.mem: use more informative signal naming for ports.
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2018-12-21 23:55:02 +00:00 |
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whitequark
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913339c04a
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hdl.ir: fix port propagation between siblings.
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2018-12-21 23:53:18 +00:00 |
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whitequark
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00ef7a78d3
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compat: provide verilog.convert shim.
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2018-12-21 13:53:06 +00:00 |
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whitequark
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fc7da1be2d
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hdl.ir: do not flatten instances or collect ports from their statements.
This results in absurd behavior for memories.
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2018-12-21 13:52:18 +00:00 |
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whitequark
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568d3c5b7d
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compat: provide Memory shim.
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2018-12-21 13:15:52 +00:00 |
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whitequark
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fa2af27bb0
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hdl.mem: ensure transparent read port model has correct latency.
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2018-12-21 13:01:08 +00:00 |
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whitequark
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48d13e47ec
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back.pysim: handle out of bounds ArrayProxy indexes.
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2018-12-21 12:32:08 +00:00 |
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whitequark
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7ae7683fed
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back.pysim: give numeric names to unnamed subfragments in VCD.
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2018-12-21 12:29:33 +00:00 |
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whitequark
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af7db882c0
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hdl.mem: use different naming for array signals.
It looks like [] is confusing gtkwave somehow.
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2018-12-21 12:26:49 +00:00 |
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whitequark
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e58d9ec74d
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hdl.mem: add simulation model for memory.
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2018-12-21 11:54:32 +00:00 |
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whitequark
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a40e2cac4b
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back.pysim: fix an issue with too few funclet slots.
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2018-12-21 10:25:28 +00:00 |
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whitequark
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c49211c76a
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hdl.mem: add tests for all error conditions.
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2018-12-21 06:07:16 +00:00 |
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whitequark
|
a061bfaa6c
|
hdl.mem: tie rdport.en high for asynchronous or transparent ports.
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2018-12-21 04:22:16 +00:00 |
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whitequark
|
8d58cbf230
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back.rtlil: more consistent prefixing for subfragment port wires.
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2018-12-21 04:21:11 +00:00 |
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whitequark
|
b0bd7bfaca
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hdl.ir: correctly handle named output and inout ports.
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2018-12-21 04:03:03 +00:00 |
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whitequark
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2b4a8510ca
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back.rtlil: implement memories.
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2018-12-21 01:55:59 +00:00 |
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whitequark
|
6d9a6b5d84
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hdl.mem: implement memories.
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2018-12-21 01:53:32 +00:00 |
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whitequark
|
6672ab2e3f
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back.rtlil: explicitly pad constants with zeroes.
I'm not sure what exactly RTLIL does when a constant isn't as long
as its bit width, and there's no reason to keep the ambiguity.
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2018-12-21 01:51:18 +00:00 |
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whitequark
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221f108fbe
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back.rtlil: fix translation of Cat.
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2018-12-21 01:48:02 +00:00 |
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whitequark
|
f7fec804ec
|
ir: allow non-Signals in Instance ports.
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2018-12-20 23:40:40 +00:00 |
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whitequark
|
8cc900c4ef
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setup: update pyvcd dependency, for var_type="string".
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2018-12-19 17:17:25 +00:00 |
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whitequark
|
0f2c7e7161
|
compat: import genlib.record from Migen.
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2018-12-18 20:04:22 +00:00 |
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whitequark
|
a90748303c
|
compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.
|
2018-12-18 20:03:32 +00:00 |
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whitequark
|
dbbcc49a71
|
hdl.ast: Cat.{operands→parts}
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2018-12-18 19:15:50 +00:00 |
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whitequark
|
4199674edd
|
back.pysim: implement *.
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2018-12-18 18:02:21 +00:00 |
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whitequark
|
07e9cfa939
|
test.sim: add tests for sync functionality and errors.
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2018-12-18 17:53:50 +00:00 |
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whitequark
|
7fa82a70be
|
back.pysim: eliminate most dictionary lookups.
This makes the Glasgow testsuite about 30% faster.
|
2018-12-18 16:36:54 +00:00 |
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whitequark
|
7341d0d7ef
|
hdl.ast, hdl.xfrm: various microoptimizations to speed up pysim.
|
2018-12-18 16:13:29 +00:00 |
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whitequark
|
c5f169988b
|
back.pysim: use arrays instead of dicts for signal values.
This makes the Glasgow testsuite about 40% faster.
|
2018-12-18 05:20:20 +00:00 |
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whitequark
|
39605ef551
|
back.pysim: naming. NFC.
|
2018-12-18 04:46:36 +00:00 |
|
|
whitequark
|
65702719e8
|
back.pysim: fix an off-by-1 in add_sync_process().
|
2018-12-18 04:43:04 +00:00 |
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whitequark
|
34b81d0b87
|
back.pysim: trigger processes waiting on Tick() exactly at clock edge.
|
2018-12-18 04:37:39 +00:00 |
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whitequark
|
d6e98fd934
|
back.pysim: continue running simulator processes until they suspend.
|
2018-12-18 03:05:16 +00:00 |
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whitequark
|
51a92bc870
|
Travis: cache Yosys installation explicitly.
|
2018-12-18 00:42:14 +00:00 |
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whitequark
|
c7f9386eab
|
fhdl.ir: add black-box fragments, fragment parameters, and Instance.
|
2018-12-17 22:55:39 +00:00 |
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whitequark
|
de6c12af77
|
Travis: build and cache Yosys.
|
2018-12-17 17:21:42 +00:00 |
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whitequark
|
8d1639a5a8
|
hdl, back: add and use SignalSet/SignalDict.
|
2018-12-17 17:21:29 +00:00 |
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whitequark
|
8c4de99c0d
|
hdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC.
|
2018-12-17 17:21:29 +00:00 |
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whitequark
|
f1e390cbc9
|
back.rtlil: update for Yosys master.
|
2018-12-17 15:50:43 +00:00 |
|
|
whitequark
|
850674637a
|
back.rtlil: implement Array.
|
2018-12-17 01:15:23 +00:00 |
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|
whitequark
|
87cd045ac3
|
back.rtlil: implement Part.
|
2018-12-17 01:05:08 +00:00 |
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|
whitequark
|
f968678937
|
back.rtlil: handle reset_less domains.
|
2018-12-16 23:52:47 +00:00 |
|
|
whitequark
|
015998eba9
|
hdl.dsl: add clock domain support.
|
2018-12-16 23:51:24 +00:00 |
|
|
whitequark
|
b2f828387a
|
hdl.dsl: cleanup. NFC.
|
2018-12-16 23:44:00 +00:00 |
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|
whitequark
|
91b7561a00
|
back.rtlil: extract _StatementCompiler. NFC.
|
2018-12-16 22:26:58 +00:00 |
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|
whitequark
|
b9a0af8bde
|
back.rtlil: simplify. NFC.
|
2018-12-16 21:00:00 +00:00 |
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