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Catherine 78b90fbafa build.plat,vendor: fix toolchain environment variable check. 
The bug was introduced in commit 15b6068c. A changelog entry was also
missing.

Fixes #1089.
 2024-02-08 11:37:59 +00:00
Daniel Estévez d8f70be4d9 xilinx: use FDPE instances to implement get_async_ff_sync() 
This closes #721 by implementing get_async_ff_sync() using FDPE
primitives to obtain exactly the netlist that we want. This consits
of a chain of N FPDEs (by default N = 2) with all their PRE pins
connected to the reset for a positive edge reset or to the ~reset
for a negative edge reset. The D pin of the first FDPE in the chain
is connected to GND.

To make timing analysis work correctly, two new attributes are
introduced: amaranth.vivado.false_path_pre and
amaranth.vivado.max_delay_pre. These work similarly to
amaranth.vivado.false_path and amaranth.vivado.max_delay, but affect
only the PRE pin, which is what is needed for this synchronizer.
The TCL has been modified to generate constraints using these
attributes, and there are comments explaining how to use the attributes
directly in an XDC file in case the user wants to manage their XDC
file manually instead of using the TCL.
 2024-02-08 11:30:51 +00:00
Catherine 9e75962c35 Implement RFC 27: Testbench processes for the simulator. 
Co-authored-by: Wanda <wanda@phinode.net>
 2024-02-06 23:12:07 +00:00
Wanda f48b8650c4 sim: fix simulation loop when process catches an injected exception. 2024-02-06 18:55:11 +00:00
Catherine 15b6068c57 Remove features deprecated in past releases. 2024-02-06 15:55:05 +00:00
Vegard Storheil Eriksen 5e2f3b7992 Implement RFC 42: Const from shape-castable. 2024-02-06 10:18:12 +00:00
Wanda 089213e19f Implement RFC 46: Change Shape.cast(range(1)) to unsigned(0). 2024-02-06 10:05:10 +00:00
Catherine 1fe7bd010f hdl: remove subclassing of AnyValue and Property. 
This subclassing is unnecessary and makes downstream code more complex.
In the new IR, they are unified into cells with the same name anyway.
Even before that, this change simplifies things.
 2024-02-05 05:58:12 +00:00
Wanda 115954b4d9 lib.fifo: add Memory as submodules instead of its ports. [NFC] 
This makes the generated netlist very slightly nicer.
 2024-01-31 21:14:08 +00:00
Catherine b5f0295bf4 docs/changes: mention removal of Repl. 2024-01-31 04:13:31 +00:00
Catherine 357ffb680c hdl: remove Repl per RFC 10. 
Closes #770.
 2024-01-31 03:01:35 +00:00
Catherine 4da8adf7ba back.rtlil: remove _SyncBuilder. NFC 
Amaranth doesn't emit sync rules for a while since these are private
for the Yosys Verilog frontend.
 2024-01-31 02:47:52 +00:00
Catherine 572a60d838 hdl: add missing compatibility shims. 
These were originally planned to be committed as a part of 5dd1223c,
but were lost during rebasing.
 2024-01-31 02:05:17 +00:00
Wanda 1506f08b81 sim: use Value.cast on traces. 
See kuznia-rdzeni/coreblocks#357.
 2024-01-30 23:20:31 +00:00
Catherine ea3d6c9557 docs/reference: document compat guarantee, importing, shapes. 
This commit also contains a related semantic change: it adds `Shape`
and `ShapeCastable` to the `__all__` list in `amaranth.hdl`. This is
consistent with the policy that is laid out in the new documentation,
which permits such additions without notice.

Co-authored-by: mcclure <mcclure@users.noreply.github.com>
 2024-01-30 22:54:18 +00:00
Catherine c9b87a4fc5 docs: lang.rst→guide.rst, add reference.rst. 2024-01-30 22:54:18 +00:00
Catherine 5dd1223cf8 amaranth.hdl: start all private names with an underscore. 
This change completes commit 9dc0617e and makes all the tests pass.
It corresponds with the ongoing langauge reference documentation effort.

Fixes #781.
 2024-01-30 17:20:45 +00:00
Catherine cf83193bf9 amaranth.hdl: rename internal modules to begin with an underscore. 
This change completely breaks the library. It is done separately just
to make sure git tracks renames as such.
 2024-01-30 17:20:45 +00:00
Catherine e88ff1335e docs/start: update to track changes in the language. 2024-01-30 03:22:46 +00:00
Catherine 8678d5fa14 hdl.dsl: warn if a case is defined after a default case. 2024-01-30 02:54:48 +00:00
Wanda e9299ccd0e hdl.ast: change warning on out-of-range reset to an error, improve it. 
Fixes #1019.
 2024-01-30 02:35:26 +00:00
Catherine 8501d9dd73 docs/changes: fix formatting. 2024-01-29 19:33:39 +00:00
Catherine fc7c86bbe6 docs/changes: link to docs for past releases. 2024-01-29 19:33:39 +00:00
Catherine 65d77f03fe back.verilog: forbid Yosys version range with dangling else bug. 
Fixes #1049.
 2024-01-24 16:45:22 +00:00
Catherine 0ea2aa6b69 docs/lang: document arrays. 2024-01-22 23:25:14 +00:00
Catherine 53f7b628b3 docs/lang: document instances. 2024-01-22 23:25:14 +00:00
Catherine a5dd63246c docs/lang: document domain renaming. 2024-01-22 23:25:14 +00:00
Catherine b3639c4cc5 utils: fix docstring syntax. 2024-01-22 23:25:14 +00:00
Adam Greig db7e64960c lib.crc: make module documentation introduction consistent with other stdlib modules. 2024-01-19 08:57:57 +00:00
Wanda b40c18fb00 hdl.ast: suggest bit_select or word_select when indexing with Value. 
Fixes #1044.
 2024-01-18 20:06:55 +00:00
Wanda 9e9790377a back.rtlil: fix emitting ROMs 2024-01-18 06:40:12 +00:00
Catherine 6211eca4ac docs: update cover, title, and copyright. 2024-01-17 18:29:16 +00:00
Wanda ae36b596bb hdl.mem: Switch to first-class IR representation for memories. 
Fixes #611.
 2024-01-17 08:10:28 +00:00
Wanda 2fecd1c78b examples.basic.pmux: Fix for RFC 39. 2024-01-16 12:14:43 +00:00
Catherine 95538a3e07 docs/lang: describe ResetInserter and EnableInserter. 
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
 2024-01-15 23:30:05 +00:00
Catherine be0e163279 docs/lang: clarify some text about clock domains. 
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
 2024-01-15 23:30:05 +00:00
Catherine b8ca2a09b4 docs: make the logo a bit smaller. 
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
 2024-01-15 23:30:05 +00:00
Wanda bf8faea51e hdl.ast: raise a sensible error for xxx in Value 2024-01-14 00:36:44 +00:00
Wanda 86d14f584e Implement RFC 39: Change semantics of no-argument m.Case(). 2024-01-13 22:33:54 +00:00
Wanda eb1c55859e hdl.ir: collect source location for Instance. 2024-01-13 22:33:01 +00:00
Wanda 7f76914b74 Implement RFC 17: Remove log2_int. 
Reexports of `amaranth.utils` functions are removed from
`amaranth._utils` to avoid a circular import issue (for `deprecated`).
Since this is a private module, this should not be a problem.
 2024-01-11 04:45:17 +00:00
Wanda ea258fad71 Change uses of Case() to Default() in preparation for RFC 39. 2024-01-11 04:44:02 +00:00
Wanda 7e18786c97 hdl.ast: use operator.index instead of int. 
This ensures things like `Const(1.5)` raise an error.

`int(operator.index())` is used since `operator.index(True)` on Python
3.9 and earlier returns `True` instead of `1`.
 2024-01-10 18:07:48 +00:00
Wanda f25bf51a92 hdl.dsl: fix handling of redundant Case branches. 
Fixes #1024.
 2024-01-10 18:04:06 +00:00
Catherine d8515807c2 docs: explain elaboration, elaboratables, and submodules. 
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
 2024-01-09 22:32:14 +00:00
Catherine 4e1b2451ec build.run: use correct working directory in BuildPlan.execute_local. 
This regression was introduced in commit 3200a3961. Fixes #1020.
 2024-01-09 15:55:54 +00:00
Catherine e59e2aa715 build.plat: add trailing newline at end of build script. 2024-01-09 15:55:54 +00:00
Jaro Habiger ded84fe9d6 sim: fix ValueCastable not being recognized as a coroutine command 2024-01-05 14:30:38 +00:00
Catherine 4014aef033 docs: change mobile navbar color too. 2024-01-05 12:28:22 +00:00
Piotr Esden-Tempski 7eea9c39cf docs: fix nav-bar on mobile 
The side nav-bar tweaks should only be valid when the side nav bar is present. It is only present on displays wider than 769px.
 2024-01-04 20:14:07 +00:00