Commit graph

11 commits

Author SHA1 Message Date
whitequark 7e2b72826f sim.core: warn when driving a clock domain not in the simulation.
Closes #566.
2021-12-11 13:22:24 +00:00
whitequark ac13a5b3c9 sim._pyrtl: reject very large values.
A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.

This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.

Fixes #588.
2021-12-11 13:00:46 +00:00
whitequark 66295fa388 sim.pysim: refuse to write VCD files with whitespace in signal names.
Closes #595.
2021-12-11 11:12:25 +00:00
whitequark b452e0e871 hdl.ast: support division and modulo with negative divisor.
Fixes #621.

This commit bumps the Yosys version requirement to >=0.10.
2021-12-11 10:25:48 +00:00
whitequark 909a3b8be7 Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00
whitequark e88d283ed3 hdl.ast: simplify Mux implementation. 2021-10-02 14:18:02 +00:00
Robin Ole Heinemann 25caf4045b *: remove unused imports 2021-05-18 20:18:55 +00:00
Marcelina Kościelnicka 44318149e0
sim._pyrtl: mask Mux selection operand.
Otherwise it behaves funny when it's eg. the result of operator ~.
2020-11-14 15:22:34 +00:00
whitequark df70aae887 sim._pyrtl: sign extend RHS of assignment.
Fixes #502.
2020-10-22 16:08:38 +00:00
whitequark b65e11f38f sim: split into base, core, and engines.
Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.

This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.

This commit completely rearranges simulation code.
  1. sim._base defines internal simulation interfaces. The clarity of
     these internal interfaces is important because simulation
     engines mix and match components to provide a consistent API
     regardless of the chosen engine.
  2. sim.core defines the external simulation interface: the commands
     and the simulator facade. The facade provides a single entry
     point and, when possible, validates or lowers user input.
     It also imports built-in simulation engines by their symbolic
     name, avoiding eager imports of pyvcd or ctypes.
  3. sim.xxxsim (currently, only sim.pysim) defines the simulator
     implementation: time and state management, process scheduling,
     and waveform dumping.

The new simulator structure has none of the downsides of the old one.

See #324.
2020-08-27 11:52:31 +00:00
whitequark 67b957d4f4 tests: move out of the main package.
Compared to tests in the repository root, tests in the package have
many downsides:
  * Unless explicitly excluded in find_packages(), tests and their
    support code effectively become a part of public API.
    This, unfortunately, happened with FHDLTestCase, which was never
    intended for downstream use.
  * Even if explicitly excluded from the setuptools package, using
    an editable install, or setting PYTHONPATH still allows accessing
    the tests.
  * Having a sub-package that is present in the source tree but not
    exported (or, worse, exported only sometimes) is confusing.
  * The name `nmigen.test` cannot be used for anything else, such as
    testing utilities that *are* intended for downstream use.
2020-08-27 00:33:31 +00:00
Renamed from nmigen/test/test_sim.py (Browse further)