Using 'x is legal RTLIL, in theory, but in practice it crashes Yosys
and when it doesn't, it causes Yosys to produce invalid Verilog.
Using a dummy wire is always safe and is not a major readability
issue as this is a rare corner case.
(It is not trivial to shorten the RHS in this case, because during
expansion of an ArrayProxy, match_shape() could be called in
a context far from the RHS handling logic.)
The elaboratable is already likely driving the clk/rst signals in
some way appropriate for the platform; if we expose them as ports
nevertheless it will cause problems downstream.
This pattern usually produces an extremely hard to notice bug that
will usually break a design when it is triggered, but will also be
hidden unless the pathological value of a boolean switch is used.
Fixes#159.
This might help with propagation of locations through optimizer
passes, since not all of them take care to preserve cells at all,
but usually wires stay intact when possible.
Also fixes incorrect source location on value.part().
Before this commit, it was a print statement, and therefore, command
interpreter options like -Wignore did not affect it. There is no API
to access the warning filter list, so it was turned into a real
warning; and further, since Python 3.6, tracemalloc can be used
as a standard method to display traceback to allocation site instead
of the ad-hoc traceback logic that was used in Elaboratable before.
This gives particularly pathological results on IO buffers, like:
connect \D_OUT_0 \user_led_0_user_led_0__o
Since subfragment signals are name-prefixed because this works well
for signals propagated upwards across hierarchy, this is never
desirable for instances.
This is useful when most attributes in a large composite resource
are the same, but a few signals are different, and also when building
abstractions around resources.
Fixes#128.
This primarily fixes the problem with source location precision in
Module (which used to trace locations from __exit__ of the context
managers, by which point everything interesting has been lost), but
also improves memory port and control inserter source locations.
On the sample of examples/basic/*.py, the only incorrectly inferred
remaining location is clk pointing to hdl/mem.py:166.
