whitequark
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621dddebfd
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hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.
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2018-12-22 22:19:14 +00:00 |
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whitequark
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68dae9f50e
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hdl.ir: flatten hierarchy based on memory accesses, too.
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2018-12-22 21:43:46 +00:00 |
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whitequark
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ae0cb48fbb
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hdl.xfrm: implement LHSGroupAnalyzer.
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2018-12-22 06:58:24 +00:00 |
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whitequark
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f6772759c8
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hdl.ir: fix port propagation between siblings, in the other direction.
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2018-12-22 00:31:31 +00:00 |
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whitequark
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913339c04a
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hdl.ir: fix port propagation between siblings.
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2018-12-21 23:53:18 +00:00 |
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whitequark
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fa2af27bb0
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hdl.mem: ensure transparent read port model has correct latency.
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2018-12-21 13:01:08 +00:00 |
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whitequark
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48d13e47ec
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back.pysim: handle out of bounds ArrayProxy indexes.
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2018-12-21 12:32:08 +00:00 |
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whitequark
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e58d9ec74d
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hdl.mem: add simulation model for memory.
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2018-12-21 11:54:32 +00:00 |
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whitequark
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c49211c76a
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hdl.mem: add tests for all error conditions.
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2018-12-21 06:07:16 +00:00 |
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whitequark
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b0bd7bfaca
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hdl.ir: correctly handle named output and inout ports.
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2018-12-21 04:03:03 +00:00 |
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whitequark
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f7fec804ec
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ir: allow non-Signals in Instance ports.
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2018-12-20 23:40:40 +00:00 |
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whitequark
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dbbcc49a71
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hdl.ast: Cat.{operands→parts}
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2018-12-18 19:15:50 +00:00 |
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whitequark
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4199674edd
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back.pysim: implement *.
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2018-12-18 18:02:21 +00:00 |
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whitequark
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07e9cfa939
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test.sim: add tests for sync functionality and errors.
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2018-12-18 17:53:50 +00:00 |
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whitequark
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c7f9386eab
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fhdl.ir: add black-box fragments, fragment parameters, and Instance.
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2018-12-17 22:55:39 +00:00 |
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whitequark
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8d1639a5a8
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hdl, back: add and use SignalSet/SignalDict.
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2018-12-17 17:21:29 +00:00 |
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whitequark
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015998eba9
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hdl.dsl: add clock domain support.
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2018-12-16 23:51:24 +00:00 |
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whitequark
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d4e8d3e95a
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back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
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2018-12-16 10:31:42 +00:00 |
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whitequark
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d9579219ee
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test.sim: generalize assertOperator. NFC.
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2018-12-15 21:08:29 +00:00 |
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whitequark
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20a04bca88
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back.pysim: implement Part.
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2018-12-15 20:58:06 +00:00 |
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whitequark
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54fb999c99
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back.pysim: implement ArrayProxy.
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2018-12-15 19:37:36 +00:00 |
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whitequark
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80c5343600
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hdl.ast: implement Array and ArrayProxy.
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2018-12-15 17:16:31 +00:00 |
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whitequark
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c6e7a93717
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hdl: appropriately rename tests. NFC.
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2018-12-15 16:13:53 +00:00 |
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whitequark
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790eb05a92
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Rename fhdl→hdl, genlib→lib.
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2018-12-15 14:25:31 +00:00 |
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whitequark
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b70340c0da
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pyback.sim: test Slice, Cat, Repl.
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2018-12-15 10:09:14 +00:00 |
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whitequark
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db4600d52b
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fhdl.ast, back.pysim: implement shifts.
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2018-12-15 09:58:30 +00:00 |
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whitequark
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46f5addf05
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fhdl.ast: refactor Operator.shape(). NFC.
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2018-12-15 09:46:20 +00:00 |
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whitequark
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f9f7921959
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fhdl.ir: test iter_comb(), iter_sync() and iter_signals().
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2018-12-15 09:26:36 +00:00 |
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whitequark
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f5e8c9033d
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fhdl.ir: fix incorrect uses of positive to say non-negative.
Also test Part and Slice properly.
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2018-12-15 09:26:23 +00:00 |
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whitequark
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2001359b66
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fhdl.ir: automatically flatten hierarchy to resolve driver conflicts.
Fixes #5.
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2018-12-14 22:48:17 +00:00 |
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whitequark
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579feaba4e
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fhdl.ir: Fragment.{drive→add_driver}
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2018-12-14 20:58:29 +00:00 |
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whitequark
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50ba443f92
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fhdl.ast: fix Switch with constant test.
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2018-12-14 16:09:51 +00:00 |
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whitequark
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9307a31678
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back.pysim: Simulator({gtkw_signals→traces}=).
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2018-12-14 15:23:22 +00:00 |
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whitequark
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474d46ced8
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back.pysim: implement most operators and add tests.
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2018-12-14 14:21:22 +00:00 |
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whitequark
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7d91dd56c8
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fhdl.xfrm: implement DomainLowerer.
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2018-12-14 10:56:53 +00:00 |
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whitequark
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fb27c2520b
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back.pysim: new simulator backend (WIP).
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2018-12-13 18:02:46 +00:00 |
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whitequark
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71f1f717c4
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fhdl.cd: rename ClockDomain signals together with domain.
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2018-12-13 15:24:55 +00:00 |
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whitequark
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07c818e077
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fhdl.ir: move Fragment prepare logic from back.rtlil.
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2018-12-13 14:34:07 +00:00 |
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whitequark
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90f1503c91
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fhdl.ir: record port direction explicitly.
No point in recalculating this in the backend when writing RTLIL or
Verilog port directions.
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2018-12-13 13:12:31 +00:00 |
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whitequark
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9661e897e6
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fhdl.ir: a subfragment's input that we don't drive is also our input.
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2018-12-13 11:50:56 +00:00 |
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whitequark
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b150f1915d
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fhdl.ir: don't crash propagataing ports in empty fragments.
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2018-12-13 11:25:49 +00:00 |
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whitequark
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72257b6935
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fhdl.ir: implement clock domain propagation.
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2018-12-13 11:01:03 +00:00 |
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whitequark
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c5087edfa5
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fhdl.cd: add tests.
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2018-12-13 09:19:16 +00:00 |
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whitequark
|
9bee90f1bd
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fhdl.xfrm: implement DomainRenamer.
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2018-12-13 08:57:14 +00:00 |
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whitequark
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8963ab5d9f
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fhdl.xfrm: add test for ControlInserter with subfragments.
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2018-12-13 08:45:10 +00:00 |
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whitequark
|
19aa404628
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fhdl.xfrm: add tests for ResetInserter, CEInserter.
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2018-12-13 08:39:02 +00:00 |
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whitequark
|
b1a89ef5fd
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fhdl.ir: add tests for port propagation.
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2018-12-13 08:09:39 +00:00 |
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whitequark
|
a797e27573
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fhdl.dsl: add tests for lowering. 99% branch coverage.
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2018-12-13 07:33:59 +00:00 |
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whitequark
|
e0a81edf4d
|
fhdl.dsl: add tests for submodules.
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2018-12-13 07:24:28 +00:00 |
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whitequark
|
932f1912a2
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fhdl.dsl: use less error-prone Switch/Case two-level syntax.
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2018-12-13 07:11:06 +00:00 |
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whitequark
|
f70ae3bac5
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fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
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2018-12-13 06:06:51 +00:00 |
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whitequark
|
f0f4c0ce61
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fhdl.ast: bits_sign→shape.
|
2018-12-13 02:06:58 +00:00 |
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whitequark
|
dc486ad8b9
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fhdl.ast: add tests for most logic.
|
2018-12-13 02:06:55 +00:00 |
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