Commit graph

17 commits

Author SHA1 Message Date
Wanda a725282751 sim.pysim: Only close VCD/GTKW files if we opened them ourselves.
Fixes #1107.
2024-02-27 07:42:39 +00:00
Wanda 890e099ec3 Implement RFC 45: Move hdl.Memory to lib.Memory. 2024-02-19 22:24:58 +00:00
Wanda 24a392887a Implement RFC 43: Rename reset= to init=. 2024-02-15 22:52:24 +00:00
Catherine 9aebf49565 sim.pysim: only import pyvcd when needed.
In some environments (e.g. Pyodide) it may be advantageous to not load
this library, and with the import at file level, it makes the entire
simulator unusable, not just `PySimEngine.write_vcd`.

This might also help people whose Python environments are unusually
broken, whom we've historically accommodated.
2024-02-13 07:31:53 +00:00
Wanda 05ac36751a sim: prefix fields with \.
Fixes #1001.
2024-02-09 21:15:34 +00:00
Wanda b6c5294e50 hdl.MemoryInstance: refactor and add first-class simulation support. 2024-02-09 17:36:15 +00:00
Wanda 1506f08b81 sim: use Value.cast on traces.
See kuznia-rdzeni/coreblocks#357.
2024-01-30 23:20:31 +00:00
Catherine 5dd1223cf8 amaranth.hdl: start all private names with an underscore.
This change completes commit 9dc0617e and makes all the tests pass.
It corresponds with the ongoing langauge reference documentation effort.

Fixes #781.
2024-01-30 17:20:45 +00:00
Wanda 28139f5f4b sim: disambiguate duplicate names of traced signals
Fixes #976.
2023-12-03 00:51:35 +00:00
Catherine b0b193f1ad sim.pysim: admit non-signals in write_vcd(traces=...).
Rather than requiring each additional requested trace to be a signal,
all of the signals in the provided value are added to the GTKW file and
to the VCD file if they are not already there. This improves usability
for `lib.data` as struct fields can now be added to traces.
2023-11-28 12:21:21 +00:00
Catherine 4bfe2cde6f sim: add support for dumping structure fields in VCD.
See #790.

This commit adds an entirely private API for describing formatting of
values that is used in the standard library, in departure from our
standing policy of not using private APIs in the standard library.

This is a temporary measure intended to get the version 0.4 released
faster, as it has been years in the making. It is expected that this
API will be made public in the version 0.5 after going through the usual
RFC process.

This commit only adds VCD lines for fields defined in `lib.data.Layout`
when using `sim.pysim`. The emitted RTLIL and Verilog remain the same.
It is expected that when `sim.cxxsim` lands, RTLIL/Verilog output will
include aliases for layout fields as well.

The value representation API also handles formatting of enumerations,
with no changes visible to the designer. The implementation of
`Signal(decoder=)` is changed as well to use the new API, with full
backwards compatibility and no public API changes.

Co-authored-by: Wanda <wanda@phinode.net>
2023-11-27 19:03:13 +00:00
Catherine 79adbed313 sim.pysim: move name extractor functionality to Fragment.
At the moment there are two issues with assignment of names in pysim:
1. Names are not deduplicated. It is possible (and frequent) for names
   to be included twice in VCD output.
2. Names are different compared to what is emitted in RTLIL, Verilog,
   or CXXRTL output.

This commit fixes issue (1), and issue (2) will be fixed by the new IR.
2023-11-25 06:26:36 +00:00
Catherine f9da3c0d16 Pyupgrade to 3.8+. NFCI 2023-11-14 13:07:21 +00:00
Irides 538c14116c sim.pysim: use "bench" as a top level root for testbench signals.
Fixes #561.
2021-12-16 15:46:05 +00:00
modwizcode 1ee2482c6b sim: represent time internally as 1ps units
Using floats to represent simulation time internally isn't ideal
instead use 1ps internal units while continuing to use a floating
point based interface for compatibility.

Fixes #535.
2021-12-13 08:15:11 +00:00
whitequark 66295fa388 sim.pysim: refuse to write VCD files with whitespace in signal names.
Closes #595.
2021-12-11 11:12:25 +00:00
whitequark 909a3b8be7 Rename nMigen to Amaranth HDL. 2021-12-10 10:34:13 +00:00