amaranth

Author	SHA1	Message	Date
whitequark	e5e23644a4	hdl.{ast,dst}: directly represent RTLIL default case. This makes RTLIL mildly nicer: casez ({ \$5 , \$3 , \$1 }) 3'bzz1: \$next\o = \$7 ; 3'bz1z: \$next\o = \$9 ; 3'b1zz: \$next\o = \$11 ; - 3'bz: + default: { \$next\co , \$next\o } = \$13 ; endcase	2019-06-25 22:01:14 +00:00
whitequark	b8a61edc2f	hdl.dsl: allow adding submodules with computed name, like with domains.	2019-06-03 02:22:55 +00:00
whitequark	4948162f33	hdl.ir: rename .get_fragment() to .elaborate(). Closes #9.	2019-01-26 02:31:12 +00:00
whitequark	8c96675580	hdl.ast: add Past, Stable, Rose, Fell.	2019-01-17 04:31:27 +00:00
whitequark	011bf2258e	hdl: make ClockSignal and ResetSignal usable on LHS. Fixes #8.	2019-01-14 15:38:16 +00:00
whitequark	664b4bcb3a	hdl.dsl: cases wider than switch test value are unreachable. In `3083c1d6` they were erroneously fixed via truncation.	2019-01-13 08:51:49 +00:00
whitequark	3083c1d6dd	hdl.dsl: accept (but warn on) cases wider than switch test value. Fixes #13.	2019-01-13 08:46:28 +00:00
William D. Jones	2412650f56	hdl.dsl: Support Assert and Assume where an Assign can occur.	2019-01-02 11:17:39 +00:00
whitequark	470d66934f	hdl.dsl: add support for fsm.ongoing().	2018-12-27 16:19:01 +00:00
whitequark	35a44f017f	hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too.	2018-12-26 12:42:43 +00:00
whitequark	934546e633	hdl.dsl: provide generated values for FSMs.	2018-12-26 12:39:05 +00:00
whitequark	54e3195dcb	hdl.dsl: implement FSM.	2018-12-26 08:55:04 +00:00
whitequark	8d1639a5a8	hdl, back: add and use SignalSet/SignalDict.	2018-12-17 17:21:29 +00:00
whitequark	015998eba9	hdl.dsl: add clock domain support.	2018-12-16 23:51:24 +00:00
whitequark	c6e7a93717	hdl: appropriately rename tests. NFC.	2018-12-15 16:13:53 +00:00

15 commits