On Python <3.10, classes without annotations do not get an
`__annotations__` member at all, so the `getattr` on a subclass falls
back to the parent class `__annotations__`, attempting to create
signature members twice. Fix that by looking at the `__dict__` instead.
While the capability of providing signatures for components that are not
parametric is useful, most Amaranth gateware is heavily parameterized,
and the capability is not worth making most subclasses Liskov-incompatible
with the base class (where the derived class would not provide `signature`
as a class method anymore).
This was introduced in commit 44711b7d, and was never used within
Amaranth itself. While technically a breaking change I think this
will not cause enough breakage to warrant a deprecation cycle
(nor can we make this a deprecation this without a lot of work).
The attribute sees essentially no use and the information is much
better served by putting it in the module name. In addition this
means that the entire tree can be renamed simply by renaming the top
module.
Tools like GTKWave show the names of the instances, not the modules,
so they are not affected by the longer names.
`.git_archival.txt` and the functionality of deriving SCM version
from a GitHub generated archive is removed pending implementation of
pdm-project/pdm-backend#194.
It was thought previously (by me) that adding a wire that does
nothing to an empty subfragment is enough to prevent it from being
treated as a blackbox. This is enough for Yosys but not Vivado.
Another workaround could probably be used that satisfies both, but
instead let's just not translate any empty subfragments.
This doesn't account for the case of the empty toplevel, but that
does not seem worth addressing.
Fixes#899.
Tracking #879.
The directions of signals in `Pin` make it convenient to use a pin
signature in a component, such as in:
class LEDDriver(Component):
pins: Out(Signature({"o": Out(1)}))
led_driver = LEDDriver()
connect(led_driver.pins, platform.request("led"))
The `platform.request` call, correspondingly, returns a flipped `Pin`
object.
The design decision of using split memory ports in the internal
representation (copied from Yosys) was misguided and caused no end
of misery. Remove any uses of `$memrd`/`$memwr` and lower memories
directly to a combined memory cell, currently the RTLIL one.
