whitequark
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1f1aa7f468
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Add LICENSE.
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2018-12-13 07:51:49 +00:00 |
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whitequark
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48330f8742
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setup: check Python version.
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2018-12-13 07:47:07 +00:00 |
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whitequark
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a797e27573
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fhdl.dsl: add tests for lowering. 99% branch coverage.
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2018-12-13 07:33:59 +00:00 |
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whitequark
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d2e2d00e45
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fhdl.cd: rename ClockDomain.{reset→rst}.
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2018-12-13 07:27:27 +00:00 |
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whitequark
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e0a81edf4d
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fhdl.dsl: add tests for submodules.
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2018-12-13 07:24:28 +00:00 |
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whitequark
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932f1912a2
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fhdl.dsl: use less error-prone Switch/Case two-level syntax.
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2018-12-13 07:11:06 +00:00 |
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whitequark
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f70ae3bac5
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fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
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2018-12-13 06:06:51 +00:00 |
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whitequark
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5b8708017e
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fhdl.ast: fix Switch._?hs_signals() for switch without statements.
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2018-12-13 05:00:44 +00:00 |
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whitequark
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4e32f6b8de
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back.verilog: detect undriven public wires using Yosys.
This should never happen, and is certainly a logic bug in nMigen.
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2018-12-13 04:59:48 +00:00 |
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whitequark
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27d3dfc453
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back.rtlil: fix swapped operands in sync assign.
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2018-12-13 04:34:22 +00:00 |
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whitequark
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6c7f98e964
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back.rtlil: explain logic for CD reset insertion.
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2018-12-13 03:51:00 +00:00 |
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whitequark
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2c67a620ee
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back.rtlil: explicitly set the top module.
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2018-12-13 03:50:04 +00:00 |
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whitequark
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4df5c5de65
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fhdl.ir: explain how port enumeration works.
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2018-12-13 03:31:13 +00:00 |
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whitequark
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f86ec1e7ef
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back.rtlil: explain how RTLIL conversion works.
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2018-12-13 03:22:01 +00:00 |
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whitequark
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bfd0011aee
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fhdl.ir: make sure clocks and resets of used CDs appear as inputs.
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2018-12-13 02:43:22 +00:00 |
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whitequark
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a17a9e355d
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back.rtlil: give clocks and resets nicer names.
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2018-12-13 02:43:02 +00:00 |
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whitequark
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22c76e5f90
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compat.fhdl.module: implement finalization.
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2018-12-13 02:36:15 +00:00 |
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whitequark
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b42620e490
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back.rtlil: match shape of $mux ports A/B/Y.
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2018-12-13 02:35:46 +00:00 |
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whitequark
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17767642be
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tracer: add support for Python 3.7.
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2018-12-13 02:20:00 +00:00 |
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whitequark
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f0f4c0ce61
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fhdl.ast: bits_sign→shape.
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2018-12-13 02:06:58 +00:00 |
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whitequark
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dc486ad8b9
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fhdl.ast: add tests for most logic.
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2018-12-13 02:06:55 +00:00 |
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whitequark
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e45e7f1608
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Measure test coverage.
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2018-12-13 02:04:23 +00:00 |
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whitequark
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b4dab74b2e
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compat.fhdl.{module,structure}: import/wrap Migen code (WIP).
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2018-12-12 15:47:34 +00:00 |
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whitequark
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356852a570
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compat.fhdl.bitcontainer: import/wrap Migen code.
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2018-12-12 15:22:34 +00:00 |
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whitequark
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1d4d00aac6
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fhdl.ast.Signal: implement .like().
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2018-12-12 14:43:19 +00:00 |
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whitequark
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ad9b45adcd
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fhdl.ir: fix port threading code.
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2018-12-12 13:00:50 +00:00 |
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whitequark
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0fac1f8d0f
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fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
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2018-12-12 12:38:24 +00:00 |
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whitequark
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00f0b950f6
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fhdl.ast.Signal: fix typo.
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2018-12-12 12:37:30 +00:00 |
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whitequark
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aab01d9e59
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fhdl.ast.Signal: implement attrs field.
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2018-12-12 11:30:40 +00:00 |
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whitequark
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c05c189ece
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genlib.cdc.MultiReg: self.regs should be a private field.
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2018-12-12 10:52:32 +00:00 |
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whitequark
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4eadc1629a
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fhdl.ast.Signal: implement width derivation from min/max.
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2018-12-12 10:43:09 +00:00 |
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whitequark
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bc60631d68
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genlib.cdc.MultiReg: pull in from Migen.
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2018-12-12 10:12:35 +00:00 |
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whitequark
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263d577323
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fhdl.ast.Signal: implement reset_less signals.
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2018-12-12 10:11:16 +00:00 |
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whitequark
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1d46ffb591
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fhdl.ast.Signal: assign an internal name if tracer fails.
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2018-12-12 10:08:56 +00:00 |
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whitequark
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6d5878a0ee
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fhdl.dsl: allow f.sync["dom"] as a synonym of f.sync.dom.
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2018-12-12 10:00:00 +00:00 |
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whitequark
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851ed06769
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ClockDomain.{rst→reset}, for consistency with ResetInserter.
nmigen.compat.ClockDomain would alias this, for Migen compatibility.
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2018-12-12 09:49:02 +00:00 |
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whitequark
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4d3258013d
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Initial commit.
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2018-12-12 03:18:44 +00:00 |
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