Commit graph

1673 commits

Author SHA1 Message Date
Wanda
85bb5ee77c hdl._dsl: Change FSM codegen to avoid mutating AST nodes.
Fixes #1066.
2024-02-27 16:20:25 +00:00
Wanda
f524dd041a lib.io, build.res: Make Pin and related objects interfaces.
Fixes #1040.
2024-02-27 11:40:25 +00:00
Wanda
c30585b47b back.rtlil: Emit proper source location for port-signals. 2024-02-27 11:06:42 +00:00
Wanda
1cb9d43841 back.rtlil: Remove code allowing internal yosys cells in Instance.
This was allowed only because Amaranth used it internally. Now that
all uses are gone, let's just disallow it entirely.
2024-02-27 10:34:30 +00:00
Catherine
6dc7c2718c docs/guide: fix a bunch of TODOs. 2024-02-27 09:10:29 +00:00
Catherine
77e41cc88a docs: add stub stdlib/memory, mark guide as done. 2024-02-27 09:10:29 +00:00
Wanda
751e0f4b57 ir: kill Fragment.ports 2024-02-27 08:26:30 +00:00
Wanda
a725282751 sim.pysim: Only close VCD/GTKW files if we opened them ourselves.
Fixes #1107.
2024-02-27 07:42:39 +00:00
Wanda
fc81ff17f7 hdl._ir: Improve driver-driver conflict message. 2024-02-27 06:31:27 +00:00
Wanda
ccf87c62e4 back.rtlil: strip \ from names added to name_map.
Fixes #1154.
2024-02-27 06:26:56 +00:00
Amelia Cuss
a586df89ad lib.wiring.connect: diagnostic when no connection made.
If a connect() call results in no connections being made, and it's
because there were no outputs specified at all, issue an error.
Tests enumerate cases per
https://github.com/amaranth-lang/amaranth/pull/1153#issuecomment-1962810678.

Co-authored-by: Catherine <whitequark@whitequark.org>
2024-02-25 09:33:46 +00:00
Catherine
09029cdd91 hdl._ir: remember origins of a fragment during elaboration.
This isn't expected to result in a significant increase in memory use,
so for now it's enabled by default. Elaboration chains where it is not
desired to preserve origins can delete the `origins` attribute from
the fragment and nothing will be stored.

The interface `Fragment.origins` remains private, as is the rest of
the `Fragment` interface (including itself), but it enables certain
codebases that currently use a much more invasive technique to rely on
reading a single private field.
2024-02-22 19:03:55 +00:00
Amelia Cuss
c40cfc9fb5 lib.enum: honor enum.nonmember.
Use _EnumDict._member_names to determine which members to consider.
This way we don't need to redo sunder/dunder checks, and `nonmember`s
(introduced in py3.11) are correctly excluded.

This is a defacto public API, given it remains usable from py3.8
until py3.12 inclusive.  (_member_names changes from a list to a
keys-only dict for performance reasons in py3.11, but they iterate the
same.) In current Python main (i.e. what will most likely be 3.13), a
"member_names" property is added which returns those keys.
2024-02-19 23:06:22 +00:00
Wanda
890e099ec3 Implement RFC 45: Move hdl.Memory to lib.Memory. 2024-02-19 22:24:58 +00:00
Wanda
6d65dc1366 hdl, back.rtlil: track and emit module/submodule locations. 2024-02-19 21:41:32 +00:00
Wanda
188eb8d453 back.rtlil: emit wire signedness according to Signal signedness. 2024-02-16 22:03:30 +00:00
Wanda
6058ad35cf hdl._ast: make Shape immutable and hashable.
Fixes #1127.
2024-02-16 15:21:05 +00:00
Wanda
24a392887a Implement RFC 43: Rename reset= to init=. 2024-02-15 22:52:24 +00:00
Catherine
b30c87fa3e pyproject: suppress superfluous warning. 2024-02-15 19:58:19 +00:00
Catherine
52842ee524 docs: fix link rot. 2024-02-15 19:58:19 +00:00
Wanda
e3324e1456 hdl._dsl: fix using 0-width Switch with integer keys.
Fixes #1133.
2024-02-14 19:13:14 +00:00
Wanda
5ffb48b5fb hdl._ast: fix using 0-width Switch with integer keys.
This comes up in `AssignmentLegalizer`-produced `Switch`es for
`ArrayProxy`.
2024-02-14 11:52:35 +00:00
Wanda
0ecd06a7e5 sim: fix using 0-width Switch. 2024-02-14 11:51:19 +00:00
Wanda
8033ddf05e pyproject: change yosys-yowasp requirement to match RTLIL backend. 2024-02-14 11:50:36 +00:00
Wanda
353a8ce7e3 README: add the full list of supported AMD devices. 2024-02-13 21:47:18 +00:00
Catherine
4a8dd808c3 Ensure we build sensible sdists. 2024-02-13 12:52:05 +00:00
Catherine
8677ced404 Update README. 2024-02-13 12:52:05 +00:00
Catherine
0eac9c3fd0 CI: verify package metadata on all builds. 2024-02-13 12:52:05 +00:00
Catherine
841ab94a76 CI: publish packages automatically. 2024-02-13 11:43:44 +00:00
Catherine
b9c9948038 docs: use :py: role for inline Python code, not :pc:.
I originally picked :pc: as it is short for "python code", but it is
obscure and :py: is not taken, so a much more obvious role can be used
instead. Also, we all typo :pc: as :py: all the time anyway.
2024-02-13 10:38:36 +00:00
Catherine
3cb5f63aba _toolchain.yosys: add JavaScript (Pyodide) support.
In this environment it's not feasible, or at least it's not documented
how, to distribute JavaScript code by packaging it as a wheel; only
Wasm code (as shared objects) can be distributed this way. The current
`amaranth-yosys` strategy would not work even though wheels can be
installed on Pyodide, and Yosys will need to be explicitly provided by
the environment instead.

The implementation is sufficiently generic that non-Pyodide hosts could
potentially make use of it, though it doesn't seem like any exist at
the moment.
2024-02-13 07:31:53 +00:00
Catherine
9aebf49565 sim.pysim: only import pyvcd when needed.
In some environments (e.g. Pyodide) it may be advantageous to not load
this library, and with the import at file level, it makes the entire
simulator unusable, not just `PySimEngine.write_vcd`.

This might also help people whose Python environments are unusually
broken, whom we've historically accommodated.
2024-02-13 07:31:53 +00:00
Wanda
5797643c9c docs: remove leftover TODO and warning from #1003, fix matches docs. 2024-02-13 06:23:23 +00:00
Wanda
a0c8b18546 vendor._intel: use dff instead of $dff.
Fixes #1046.
2024-02-13 06:14:59 +00:00
Catherine
3867623727 docs/reference: describe out-of-bounds behavior of bit_select/word_select. 2024-02-13 05:44:52 +00:00
Catherine
2dea83cffd docs/reference: minor fixes. 2024-02-13 05:44:52 +00:00
Wanda
1dc1d2d709 vendor.lattice_ice40: use SB_DFF instead of $dff. 2024-02-13 05:42:31 +00:00
Catherine
eebb6ec3bb back.verilog: require Yosys 0.38.
This avoids the awkward requirement due to the bug in Yosys 0.37, and
will soon be required anyway once the `$check` cell is emitted.
2024-02-13 05:27:23 +00:00
Wanda
0da439cce1 hdl._ast: deprecate ValueCastable.lowermethod. 2024-02-13 05:06:06 +00:00
Wanda
e2fd819742 hdl._ast: fix shift_right and as_signed edge cases. 2024-02-13 04:52:38 +00:00
Catherine
0056e982c5 docs/reference: document Value, ValueCastable, ValueLike.
Co-authored-by: Wanda <wanda@phinode.net>
Co-authored-by: mcclure <mcclure@users.noreply.github.com>
2024-02-13 03:22:04 +00:00
Wanda
4a3a9a90e8 hdl._nir: implement __repr__ on NIR classes. 2024-02-13 01:12:44 +00:00
Wanda
4014f6429c Implement RFC 27 amendment: deprecate add_sync_process, not add_process. 2024-02-12 18:26:48 +00:00
Wanda
2d42d649ee tests: stop using implicit ports. 2024-02-12 13:24:54 +00:00
Wanda
18e5bcd6f7 hdl._nir: fix docstring typos. 2024-02-11 16:34:12 +00:00
Catherine
84709e2f00 hdl: remove ValueKey, ValueDict, ValueSet.
These aren't used internally anymore and haven't been used in any code
published on GitHub, so they are simply removed rather than deprecated.
2024-02-11 13:50:06 +00:00
Catherine
6f44438e58 hdl._ir,hdl._nir,back.rtlil: new intermediate representation.
The new intermediate representation will enable global analyses
on Amaranth code without lowering it to another representation
such as RTLIL.

This commit also changes the RTLIL builder to use the new IR.

Co-authored-by: Wanda <wanda@phinode.net>
2024-02-11 09:03:49 +00:00
Catherine
78981232d9 hdl.xfrm: add assignment legalizer.
Co-authored-by: Wanda <wanda@phinode.net>
2024-02-11 09:03:49 +00:00
Catherine
10117607a3 build.plat: fix toolchain environment variable check, #2.
Fixes typo introduced in commit 78b90fba.
2024-02-11 08:21:06 +00:00
Wanda
05ac36751a sim: prefix fields with \.
Fixes #1001.
2024-02-09 21:15:34 +00:00